1. Home
  2. Field-Programmable Gate Arrays
  3. Problems with Spartan6 CRC calculation

Problems with Spartan6 CRC calculation

000301080904010205040303 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit

I am unsuccessfully trying to update Spartan6 CRC checksums after I make packet modifications. This is not a problem for Virtex/E/2/2P/4/5/6/7 or for Spartan3E, but Spartan6 is a different story altogether. I posted this same question on Xilinx Forums, but there have been no responses.

I know that Spartan6 packets consist of 16-bit words, unlike the 32-bit words of the other architectures listed above. UG380 also states that "The Cyclic Redundancy Check register utilizes a standard 32-bit CRC checksum algorithm." My perhaps incorrect assumption is that the polynomial is the same CRC-32C (Castagnoli) polynomial as for Virtex4/5/6/7 families. I am also assuming that only "payload words" (after the packet header) factor into the calculation, just as with the other architectures, and UG380 explicitly shows the address length as 6 bits.

Does anybody know how to calculate this correctly for Spartan6? If anyone cares to see the logic I'm trying to use, it's quite similar to what works correctly for all the other Xilinx architectures:

// begin CRC calculation uint32_t address = 0; iterator p = begin(); iterator e = end(); // CRC-32C (Castagnoli) polynomial for Virtex4/5/6/7 families boost::crc_basic crc32(0x1edc6f41, 0, 0, false, true); while(p < e) { // look up the current packet const Spartan6Packet& packet = *p++; // only process write packets with non-zero payload length if(!packet.isWrite()) continue; address = packet.getAddress(); uint32_t wordCount = packet.getWordCount(); if(wordCount == 0) continue; // CRC register write (this is what compares the expected and supplied CRC values) if(address == crcRegister) { printf("Expected CRC32: %8.8x\n", (uint32_t(packet[1]) = 1 && packet[1] == rcrcCommand) { crc32.reset(); // process packet contents } else { uint32_t j; uint32_t mask; for(uint32_t i = 1; i

Reply to
Neil Steiner
Loading thread data ...
030906010305020803050301 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit

Someone pointed out to me that the necessary information can be inferred from either of these files:

ISE/verilog/src/unisims/SIM_C> I am unsuccessfully trying to update Spartan6 CRC checksums after I

Reply to
Neil Steiner
020603020404000300040405 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit

If anybody is interested, this is the code that I inferred from the simulation model. The rest of the code will be available in Torc. From the testing that I've done it seems to work correctly. One interesting deviation in Spartan6 compared to other architectures: The Auto-CRC after the FDRI write does not reset the CRC.

/// \brief CRC class for the Spartan6 architecture. struct CRC { /// \brief Length of the CRC calculation. enum { eLen = 22 }; /// \brief CRC calculation bits. uint8_t mBits[eLen]; /// \brief CRC calculation value. uint32_t mValue; /// \brief Default constructor. CRC(void) { reset(); } /// \brief Function to clear the CRC calculation. void reset(void) { for(int32_t i = 0; i < eLen; i++) mBits[i] = 0; mValue = 0; } /// \brief Update the CRC with new data. void update(uint32_t inAddress, uint32_t inWord) { uint8_t input[eLen]; uint8_t next[eLen]; // initialize the input with the current register address and data word for(int32_t i = 21, mask = 0x20; i >= 16; i

Reply to
Neil Steiner

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.