Hello,
I am wondering if any of you have encountered a problem in which the Opencores' I2C "READ" function failed. The problem I am seeing is that when prior to the data read from the slave device, the master doesn't write the 7-bits device address and a logic HIGH (to indicate a read), specifically, the master failed to send the last logic HIGH to indicate a read. As a result the slave thinks a write operation was sent as opposed to a read operation. I am wondering if any of you have encountered something similar to this.
In order to initiate a read sequence, I first sent a write to the slave, followed by the memory address location of the slave's register, then I sent the read instruction. I checked whether wb_ack_o pin is asserted and that the TIP signal have been negated before proceeding from one command to another. Is there something else that I need to do prior to executing from one command to another (i.e. more pauses?)? Or do I need to turn on clock stretching? I thought the clock stretching is supported automatically.
I used Virtex-II Pro to implement the I2C interface. The device is communicating to a Finisar XFP. I've seen this problem occuring specifically to Finisar XFPs. In addition, I have one board that exhibit this issue regardless of the XFPs used. My goal is trying to isolate whether this is an XFP issue or how I implement the I2C cores.
Any comments and suggestions are welcomed.
Thanks,
-M