problems with FSL and Microblaze

I=B4m developing a FSL Peripheral. I=B4m having the following problem: when trying to generate the bitstream it generates the error:

ERROR:MDT - issued from TCL procedure "::hw_fsl_v20_v2_10_a::check_syslevel_settings" line 14 fsl_v20_0 (fsl_v20) - FSL_Clk is unconnected. ERROR:MDT - issued from TCL procedure "::hw_fsl_v20_v2_10_a::check_syslevel_settings" line 14 fsl_v20_1 (fsl_v20) - FSL_Clk is unconnected.

Looking at the system.mhs file I found:

BEGIN fsl_v20 PARAMETER INSTANCE =3D fsl_v20_0 PARAMETER HW_VER =3D 2.10.a END

BEGIN fsl_v20 PARAMETER INSTANCE =3D fsl_v20_1 PARAMETER HW_VER =3D 2.10.a END

But I expected to find something like:

BEGIN fsl_v20 PARAMETER INSTANCE =3D download_link PARAMETER HW_VER =3D 1.00.b PARAMETER C_EXT_RESET_HIGH =3D 0 PORT SYS_Rst =3D sys_rst PORT FSL_Clk =3D sys_clk END

I suppose this is the problem but I can=B4t just edit the file because it seems to be regenerated (missing the ports again) every time I try to generate the bitstream. Can anyone help me? Thanks

Reply to
FPGA Guy
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You can edit it when EDK is closed. This file should not be regenerated if you generate bitstream. I did it a lot.

--Wayne

Reply to
sunwei1688

Wouldn't it be better to check and make sure it is connected correctly in the Bus view? And the Port view? You can filter the ports to display All and see where everything on the FSL is going.

Reply to
motty

Editing the MHS is totally safe. There are ports that do not necessarily show up in the Ports/Bus view. For example, on the V4 the ports for the hard temac's DCR do not show up. They are necessary if you want to simulate the interface, but have nothing to do with synthesis. If you switch to the ALL view, the ports can become impossible to filter to find exactly what you were looking for.

I do most of my editing of the MHS directly and then use XPS from the command line to generate my makefiles. I then execute the makefiles from the command line as well. I'm also a huge fan of the console, versus gui :).

Yes, you do not want to edit the MHS file, even with EDK, while the project is open inside of EDK. You do not have to close EDK, just the project. The MHS is your Hardware Specification file and will change everytime you make a change in EDK for the Bus/Ports. FTR, the MSS is the Software Specification file and that is changed when you make changes under the Software settings or the Application's tab.

FPGA Guy: you can edit the MHS file in your favorite text editor, while the project is not open in EDK. Or, you can make the modifications from Ports view in EDK. Once you expand the pcore for the fsl bus, you should see the Port's listed. You can then add whatever value suits your or heart.... or whatever value will actually work.

-- Mike

Reply to
morphiend

Thanks, it worked. In reallity I discovered it alone about 10 minutes after I posted the question, but thanks anyway by your fast and acurate response :)

Reply to
FPGA Guy

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