Hi newsgroup people,
maybe someone can help me with regard to the following problem:
I am using an Altera Cyclone Device EP1C12F256C7.
When I program it via JTAG (I am not able to program it via Serial Configuration Device yet) the PLL I instantiated in the MegaWizard does run if the PLL does not have a reset input.
I have programmed a little design, some counters which are resetted. It doesn't matter whether the counters are resetted or not I cannot see anything going on at the debug pins of my FPGA.
So the question is what goes wrong.
I mean if it was a basic problem the PLL would not run. If it was exclusevely an reset problem the counters WITHOUT reset would run but they do not!
I have a watchdog which produces an asynchronous reset but then it does not get the trigger signal out of the FPGA so that the watchdog resets periodically. The trigger signal I generate in the FPGA is depedent on the counters which are NOT resettet.
Here is some piece of my trigger generation:
signal l_count : integer range 0 to 15; signal l_trigger_watchdog : std_logic;
Trigger_watchdog