Problems with Constraints (Xilinx, ISE 6.3)

So I've got the whole VHDL thing down, but I've still got some problems understanding how to set up timing constraints.

I've got a 50 MHz oscillator that I use two DCMs to turn into three clocks, 40 MHz @ 0

Reply to
Rob Gaddi
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The easy way around the constraints editor is to edit the UCF file manually and add a line like: NET "my_clock_net" PERIOD = 25 ns HIGH 50.0%;

timing,

signal,

If you're putting out clocks on pins, you should be aware that the best way to get from a global clock route to a pin output buffer is by way of the DDR flip-flop. You must instantiate these, but that pretty much gets around the problem of losing your global clock net name. I usually use FDDRRSE to generate output clocks with D0 logic high, D1 logic low, C0 internal_clock, C1 NOT internal_clock (or 180 degree internal_clock if you have it from the DCM). R and S ports can be logic low.

I've found that when you take a clock signal on a global net and attach it to more than one non-clock load, the place and route software will use a single point to get from the global net to the first non-clock load and then use (high-skew) local routing resources to route to the other loads.

Reply to
Gabor

One way is to use the Floorplanner or the FPGA editor to see what the net name is.

Don't feed clocks out like that. If you do, the phase relationship between the external clock and the internal clock depends on routing delays. Use the DDR IOB FFs to get clocks out, the timing is far better defined this way as the global clock only connects to clock inputs of FFs, and so never has to venture onto the normal routing. Figure 2 of XAPP265 shows how to do this for CLOCKOUT.

Get the name of the net as described above and put it in the UCF file. Cheers, Syms.

Reply to
Symon

Small addition, while using FPGA editor to find name or even to use as reference for constrain syntax is a good solution, it might be better if you can add a attribute to keep the signal name if possible as if not and the name keep get change every time you synthesis than you might need to redo what you do every single time you re-synthesis.

If you can't keep the name due to any reason, one trick you might consider which can be useful in many times is if possible route the signal to a spare IO as IO keep there names.

Have fun.

Reply to
Berty

If I understand the DCM documentation correctly you have to constraint only the input clock with 50 MHz. All derived clocks should get their constraints automaticely from "ngdbuild".

Somebody knows how to use a INPUT/OUTPUT OFFSET constraint with such a derived clock?

Regards Klaus

Reply to
Klaus Falser

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