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Problems in timing simulations

Hi all,

I work with ISE.6.3.3i and ModelSim 5.8c the target is a Virtex II Pro 70 -6.

My design has been P&R for two frequencies : 50 MHz and 80MHz.

In this two cases, the timing report indicates no errors and all the timing constraints were achieved. The timing constraints are essentially a PERIOD constraint and several FROM TO (all pads all FF, all pads all RAM, all FF all RAM).

But at timing simulation, some differences appear.

At the lower frequency, the design responds well to the stimuli and they were no warnings.

At 80 MHz, after my reset phasis, I see two kinds of warnings :

  1. X_FF SETUP Low VIOLATION ON I WITH RESPECT TO CLK 2. X_FF HOLD High VIOLATION ON I WITH RESPECT TO CLK

appearing at each period of the simulation and the outputs of my design aren't defined (all reds)..

My problem is that the timing report detects no errors so I don't know where to search.

Does somebody has an advice to resolve these warnings or pointers to have more informations about SETUP TIMING or HOLD TIMING ???

thank you very much for your help.

Michel

Reply to
michel leconte
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Just to clarify, you have synthesised/placed and routed twice, with different constraints, generating a 50MHz capable design, and a 80MHz capable design? i.e You aren't mixing the 50MHz and 80MHz clocks in one design?

Jeremy

Reply to
Jeremy Stringer

Just to clarify, you have synthesised/placed and routed twice, with different constraints, generating a 50MHz capable design, and a 80MHz capable design? i.e You aren't mixing the 50MHz and 80MHz clocks in one design?

Jeremy

Reply to
Jeremy Stringer

Make sure that in your testbench you are not toggling input signals too close to your clock edges.

Since you are doing a post par timing simulation (using an sdf file or similar I assume?) your TB must reflect the real world more closely and ensure that a suitable time-gap is present between clock edges and your input signal transitions.

I had the same problems in modelsim and solved it by making the testbench wait for a 1/4 clock period after an edge before supplying the next input. You may need to reflect your real system more closely than 1/4 clock period if you have detailed timing specs.

HTH,

Ken

Reply to
Ken

Thank you Ken,

your're right, I didn't adapted the data transitions relatively to the edge of my clock in the testbench. Now, during the simulations the violations has disappeared and the design responds has desired.

Another question when you say :

"I had the same problems in modelsim and solved it by making the testbench wait for a 1/4 clock period after an edge before supplying the next input. You may need to reflect your real system more closely than 1/4 clock period if you have detailed timing specs."

Does it mean that your design has an offset in constraint equal to

1/4 of the period clock ?

Michel

Reply to
michel leconte

Hi Michel,

No - the design I was working on was not destined for actual hardware so I simply used 1/4 of the clock period as a suitable value as a time buffer between my clock edges and input data transitions.

I had a half_clock_period generic in my testbench and so I could simply say for example:

wait until rising_edge(CLK); wait for HALF_CLOCK_PERIOD/2; -- supply new data now

To avoid the setup errors from the simulator.

If I had more detailed timing information relating to data coming from a device upstream of the FPGA I would have to been more diligent with how long I waited after each clock edge.....

Cheers,

Ken

Reply to
Ken

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Setup time is how long the signal must be stable before the CLK edge, hold time is how long it must be stable after. Either can be negative but the sum must be positive.

Setup violations can occur from running a design at too high a clock rate, but normally not hold violations. (That is, for a synchronous design with one clock.)

As others have indicated, it is likely that you are violating the constraints on the input. If your logic family doesn't have zero hold time, you can't change the logic inputs on the clock edge. Easiest is to change them on the opposite clock edge to the one used by the FFs.

-- glen

Reply to
glen herrmannsfeldt

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