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Problems about the synthesis(XST)

Hi, there

We are using a XUP board to implement an algorithm on FPGA right now. Our design is pretty big on the chip. The device utilization summary is listed as follows:

Logic Utilization: Number of Slice Flip Flops: 15,413 out of 27,392 56% Number of 4 input LUTs: 15,218 out of 27,392 55% Logic Distribution: Number of occupied Slices: 12,892 out of 13,696 94% Number of Slices containing only related logic: 12,892 out of

12,892 100% Number of Slices containing unrelated logic: 0 out of 12,892 0% *See NOTES below for an explanation of the effects of unrelated logic

Ever since our design grew big, some weird results appeared. And if we tried different Placer cost table in the fast_runtime.opt, we got different results. Sometimes good ones. If we optimized the design, and then shrinked it a little bit, then we could get good result without trying difference cost tables. We defined the "good result" by seeing when the maximum frequency reached 100MHz which is what we are running at.

But now, the frequency reached 101.843 MHz, the weird result still appeared. Every time I run the code, we got different result. THe simulation is just fine.

I don't really know what to do next now. I thought we shrinked the design as much as possible.

So anyone has any idea? Is it possible to use Synplify which is said to be better? Will it improve a lot?

Thanks a lot. Zhaoyi

Reply to
agou
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dear Zhaoyi PAR tools are statistical tools and never generate the same results on each run. Especially the case when the device utilization is high , You will find some nets that will not be meeting timings. You fix them by adding pipeline and next time after PAR some other nets will not be meeting timings.

To solve this problem use efficient floor planning tools like planAhead or make many runs of PAR and see results.

regards MH

Reply to
mh

I think his problem has more to do with some paths being unconstrained since the reported frequency itself meets the constraint. Another possible reason for weird behaviour is an inadequate power supply.

/Mikhail

Reply to
MM

You can get a timing report that includes unconstrained path analysis. In the properties for "generate post-place & route static timing" set "report uncovered paths" to some reasonably large number like 100. Then the timing report will have lots of lines like "unconstrained period for clock xxx", "unconstrained In Before for clock xxx", etc. This may shed some light on the problem you get in some builds.

Also the OP mentioned Synplify. This can reduce your logic size significantly, especially if you're running an older version of XST. I've noticed that XST 8.1i is significantly better than XST 6.1i for meeting area constraints on some projects. This improvement can be quite significant if the source is not written with synthesis optimization in mind.

Regards, Gabor

Reply to
Gabor

I have that problem every now and then. Sometimes it is due to unconnected logic, other times changing the optimisation helps to get the design routed. Very frustrating indeed.

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Reply to
Nico Coesel

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