Hi there - I am continuing to attempt to learn VHDL this weekend! Currently I'm trying to interface to the quadrature encoder on my Spartan 3E Starter Kit. It outputs normal quadrature signals. So, I tried to write a very simple bit of code for this purpose, which just checks which edge on which signal occurred and then checks the state of the other signal and infers if the count should be incremented or decremented from that. My code is at the bottom of my post.
In theory this method of quadrature decoding should work perfectly, unless I'm forgetting something. But for some reason which I'm afraid I don't understand this is not synthesizable. I liked the idea of using this method for quadrature decoding as it didn't require me to deal with storing the previous state - the use of the falling_edge() and rising_edge() functions did that for me. Xilinx ISE help brought me to this page:
What exactly am I doing wrong, and is there a way to fix it? Thanks so much!
-Michael
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.all;
entity hello_world is port ( clk, enc_a, enc_b : in std_logic; switches : in std_logic_vector (3 downto 0); led : out std_logic_vector (7 downto 0) ); end hello_world;
architecture rtl of hello_world is signal cnt : unsigned (30 downto 0); signal encval : unsigned (7 downto 0); signal enccnt : unsigned (7 downto 0); begin process(clk) begin if rising_edge(clk) then cnt