hi i have a custom designed board with xilinx spartan 3( xc3s400 ) with two ethernet phy layer (RTL8201) for a two port switch. I have a ring network of 10 of this board on the chain. i transmit data from the first board and count the number of packets from the last ethernet port of the tenth board to test the integrity of switch and the hdl code.
the code in some synthesis work without error but when i add another piece of code for example a counter which is unrelated to the other logics and re synthesis the code the previous parts of my code work with error.
i guess it is due to place and route section and timing constranits of ethernet phy layer. this phy layer has 2 independ transmit and receive clk and due to ease of pcb routing i connected these clk signals to normal pins not the global clk pins and now i think the timing constraints are disabled since i used this contraint on the pin NET "RTL_RXCLK" CLOCK_DEDICATED_ROUTE = "FALSE";
in timing reports it is said that all timing constraints are met but there is warning saying ?The use of
this override is highly discouraged as it may lead to very poor timing results? . what is the problem and
how can i fixed the problem ?i cannot change the pcb because of the price and time :( is it possible to check and apply timing constraints in fpga editor?
Tnx in advanced for any helpful comment Neda Baheri
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