Problem with verilog program

You are trying to use both edges of the clock AND use the clock as data. Let's focus on the first problem. The only flip flops in the FPGA that can run on both edges of the clock are found in the IO tiles. And even then, two flip flops are used--one with an inverted copy of the clock.

The second problem is that you are using the signal 'clk' as both the clock and D input of the FF. This is no good. Imagine that both signals arrive at the FF at the exact same time (and they pretty much will...even in the real world worst case). You will certainly break setup time for the flip flop and nothing will work.

Let's pretend that your code will work. What is its function? On the rising edge, the FF's Q output would equal the value of the rising edge, 1. On the negedge, the Q output of the FF would be 0. All you are doing is copying the input clock.

It seems you may need to learn a little basic digital design before attempting to model things using Verilog.

Also, it looks like you have the initial statement commented out. That is good, because it is not a good idea to use this statement for synthesis. Your synthesizer (XST) probably won't support it. I don't know if any do. If you want your logic to start at a known value, use a reset.

The error message describes the problem. A logic synthesizer works by matching your HDL code to different templates until it finds a match. The typical verilog flip-flop template is:

always @(posedge clk) b

ok, I see your point. What I wanted is to simply mimic the clock, and simulate it to see if I can see any time lag due to the clock travelling through the internals of the xilinx.

I have now changed it to this, and it worked:

module a2(clka,clkb); input clka; output clkb; wire clkb; assign clkb = clka ; endmodule

this also seemed to work, but with a lot of warnings along the way

module a2(clka,clkb); input clka; output clkb; reg clkb; always @(clka) begin clkb= !clkb; end endmodule

This will half the frequency, I suppose I cannot change clkb=!clkb to clkb=clka due to the setup time you mentioned.

BTW, do you know what exactly is the purpose of the verilog test bench waveform simulation? There are yellow spikes on the output screen, and when I click on them the clk1 signal can be changed from o to 1 etc.

You mean digital design in the context of verilog, I agree. Although I think I got the idea now pritty much, but yes, to understand the internals of the cpld will definately be beneficial.

This is a real problem.

I remember 30 years ago finding that the 74LS74 has 0ns hold time, so that one can change the input at the clock edge. Among others, this allows one to make a T-FF connecting Qbar to D. As I remember, the 7474 (without LS) didn't have that feature. I thought that Xilinx logic was supposed to have 0ns hold time, though one would have to be careful with the routing.

-- glen

(snip)

Traditionally that should be either (posedge clka) or (negedge clka).

If I understand the simulation, it should do the always block on either transition, so you don't have a divide by two. Again, I don't believe it will synthesize a dual edge FF.

-- glen

Yeah, I guess I see how you can meet a setup time depending on how you define your data. And Xilinx logic may have 0 hold time. But why would you want to use your clock input as data? There will almost certainly be a better way to do whatever it is you are trying to do. It makes my head hurt to think of all the problems that may arise.