Hi, I've a problem on fitting my vhdl design in a cyclone. The compiler report says "Required P2P time" is longer than actual "P2P time". I can find in the quartus help that we could increase T hold specification to correct this problem.. But I don't really understand what "Thold" mean.. and i'm not sure my solution is to increase it.. So, if anyone could help me to understand what happen... Many thanks..
Consider a synchronous design.
--Mike Treseler
Definitions of tHOLD, tSETUP can be found in the Static Timing Analysis Section of the Quartus Handbook. The URL is
In general when one sees the mesaage
it means
The clock skew is greater than his data delay, causing a hold violation.
To fix this try the following: i) Check that the clock feeding the destination register is using a global clock line. ii) Check that there are no gated or ripple clocks in the design. If you have a gated or ripple clock a derived clock assignment should be made. While may not necessary fix the hold issue, but will better constraint the design. iii) Finally if you can copy and paste the list_path message, we can probably give more help.
Hope this helps, Subroto Datta Altera Corp.
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