Hell
I have a design (Verilog) and using a STARTUP_SPARTAN3 instance. O
the instance, I send the clock signal and reset signal. The cloc and reset signals are comming directly from the top-level clock an reset pins
That is, I have code looking like
module counter_7seg(reset, clk, segLow, segHigh); //Top-leve modul input reset input clk output [6:0] segHigh, segLow
[...]STARTUP_SPARTAN3 Startup(.CLK(clk)
.GSR(reset))
[...When I synthesize, with Synplify 7.7.1, and I verify the technolog schematic, it get synthesize a
[code:1:7e7d529f83IBU reset------|>--------------- IBUFG BUFG +----+ +----+ clk ----|-|>-|--+--|-|>-|------... (global cloc network +----+ | +----+ | | STARTUP_SPARTAN | | +---------------- | +-|GSR | | +-------------|CLK | 0-|GTS +---------------- [/code:1:7e7d529f83
As you can see, local routing is used from the clock pin to th
startup module, while the rest of the design use global cloc networ
I do the same thing with XST (in ISE 7.1i), and it route using globa
clock line as input of the startup block
I tried many ways and can not come to correct result in Synplify
help