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Problem with PLL ?

Hi newsgroups users,

maybe someone has experienced the following problem:

I have a HDL design in which a PLL is instantiated (QuartusII).

To test the functionality of the PLL I made a smaller design containing exactly the same PLL. For the small design I have found out that the PLL does work.

When I compile my original design I can see that the PLL does not work.

As I said the pin assignments and pll assignments are exactly the same.

Where could be the problem?

Unused pins are set to ground. There are also defined input pins which are not used. Could it be that the fitter does produce some strange combintation of setting the unused input pins to ground so that some driver conflict exists ?

Thank you for your help.

Kind regards

André

Reply to
ALuPin
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Something additional:

I have found out that when I reserve all unused pins

  1. as inputs, tri-states --> PLL does not work
  2. as outputs, driving ground --> PLL does not work

  1. as output, driving an unspecified signal --> The PLL works

I do not understand why this has an influence on the PLL. I would appreciate your opinion.

Rgds André

Reply to
ALuPin

I had a similar problem with an Actel ProAsic. I just wanted to test the PLL before using it in my design, so I just connected the inputs and outputs of the PLL to pins on the FPGA. It didn't synthesize. I contacted tech. support and this person found out that I needed to drive some logic with the PLL for it to synthesize. (could be any dummy logic). And this seemed to be a peculiarity of this ProAsic+ devices, because apparently there wasn't a problem with other families (I don't know, I just have the ProAsic+)

Good luck.

ALuP>> Hi newsgroups users,

Reply to
David Corredor

Hi again,

The plot at "

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" shows the situation:

The blue plot represents the PLL output E measured at the dedicated clock output pin. The pink plot shows that the PLL does not lock (LOCKED signal does not get high). The green plot shows the input clock of the PLL.It is fed via the dedicated clock input pin. As the plot shows the PLL begins to tune but it does not lock. At the same time the voltage swing of the input signal is reduced while keeping the frequency stable.

Is it possible that neighbor pins of the dedicated input/output clock pins may be hot-wired with the clock pins (I could not find any short) ? I have defined all unused pins to "input tristated" so that in a short case there should arise no problem.

What other possibilities could be taken into consideration?

I have made a timing simulation in Modelsim and the PLL does lock.

Thank you for your help.

Kind regards

André

Reply to
ALuPin

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