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Problem with ModelSim XE

Hello Everyone, I am new to Xilinx and the whole FPGA thing and this might be a very stupid problem that I am facing. Anyways Here it goes. I am trying to write a simple counter program using ISE Webpack 7.1. I write the code using language templates (verilog)then I check the syntax and everything is fine till this point.

Then I make a testbench wave form and I can also see the expected results dialog box. Next step is I use ModelSim XE starter free version to simulate behavioural model. It opens up ModelSim automatically and this is where after running for a few seconds it stops. Below are the few messages that I am posting.......

Basically in the tfw window in ModelSim it stops at $stop;. Please see below.

Is there something that I am missing. Thanks a lot in advance. THIS IS TBCounter.tfw WINDOW

module TBCounter_3try; reg CLOCK = 1'b0; reg DIRECTION = 1'b0; wire [3:0] COUNT_OUT;

parameter PERIOD = 40; parameter real DUTY_CYCLE = 0.5; parameter OFFSET = 200;

initial // Clock process for CLOCK begin #OFFSET; forever begin CLOCK = 1'b0; #(PERIOD-(PERIOD*DUTY_CYCLE)) CLOCK = 1'b1; #(PERIOD*DUTY_CYCLE); end end

counter UUT ( .CLOCK(CLOCK), .DIRECTION(DIRECTION), .COUNT_OUT(COUNT_OUT));

integer TX_ERROR = 0;

initial begin // Open the results file... #2040 // Final time: 2040 ns if (TX_ERROR == 0) begin $display("No errors or warnings."); end else begin $display("%d errors found in simulation.", TX_ERROR); end $stop; end

initial begin // ------------- Current Time: 290ns #290; DIRECTION = 1'b1;

THIS IS IN THE TRANSCRIPTS WINDOW # Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl # do TBCounter_3try.fdo # ** Warning: (vlib-34) Library already exists at "work". # Model Technology ModelSim XE III vlog 6.0a Compiler 2004.11 Nov 10

2004 # -- Compiling module counter # # Top level modules: # counter # Model Technology ModelSim XE III vlog 6.0a Compiler 2004.11 Nov 10 2004 # -- Compiling module TBCounter_3try # # Top level modules: # TBCounter_3try # Model Technology ModelSim XE III vlog 6.0a Compiler 2004.11 Nov 10 2004 # -- Compiling module glbl # # Top level modules: # glbl # vsim -L xilinxcorelib_ver -L unisims_ver -lib work -t 1ps TBCounter_3try glbl # Loading work.TBCounter_3try # Loading work.counter # Loading work.glbl # .main_pane.mdi.interior.cs.vm.paneset.cli_0.wf.clip.cs # .main_pane.workspace # .main_pane.signals.interior.cs # No errors or warnings. # Break at TBCounter_3try.tfw line 55 # Simulation Breakpoint: Break at TBCounter_3try.tfw line 55 # MACRO ./TBCounter_3try.fdo PAUSED at line 14
Reply to
learnfpga
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$stop is a command to halt the simulation and thats the reason your simulation halts.

Reply to
Fpga_Designer

But I am not giving it anything. Once I say simulate behavioural model it automatically opens up ModelSim, Starts simulation and then tells me that simulation stopped. So I dont know whats the problem

Reply to
learnfpga

Since you are using the ISE waveform editor to create the testbench it automatically inserts that statement. Probably there would be some option in the simulation properties where you can change it.

Reply to
Fpga_Designer

The testbench generator is writing the code for you. Writing your own testbench code makes these things easier to debug.

-- Mike Treseler

Reply to
Mike Treseler

There is another thing that I wanted to ask. I have installed ISE Webpack 7.1. Doesn't it come with ISE simulator? Becasue I when I look in Process View window I only see ModelSim. Is there something I have to do to invoke ISE simulator? Thanks

Reply to
learnfpga

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Reply to
Fpga_Designer

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