Problem with Microblaze max clocking

Hi everybody, I'm using EDK 9.1i and in my design I use a Microblaze core (v

6.00.b). The device is a xc2v1000-4 (in a 2VMB1000 board from Memec Design).

In every system that I create, the maximum clocking that I can acheive is about 80MHz because of DCACHE_FSL_OUT_CLK signal. Looking in the time information of the design report i see that the maximum clock for such signal is never more than 80.270MHz and if I try to use an higher clocking, the microcontroller doesn't start.

In the past I have already programmed the same device (of the same board) but with previous versions of microblaze I acheived up to

120MHz.

In my design I don't use cache so that the DCACHE_FSL_OUT_CLK is useless, but even if it is not used by the design it limits the clocking. I don't have time constraints in my ucf file.

Is it possible to workaround this problem? The device is capable to reach higher clocking but with this version of Microblaze core it seems limited.... surely I'm missing something but I don't understand what...

Any idea?

Thank's a lot, Andrea.

Reply to
Andrea05
Loading thread data ...

If you add a TIG timing constraint to your UCF (see your constraints guid for details) for the specific path that's failing timing, you may be able to get improved timing.

Reply to
John_H

Hi,

If you provided with your settings of MicroBlaze from the .mhs file, I can have a look at see if there is something that can be trimmed.

Göran

Reply to
Göran Bilski

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.