So my simulations aren't coming out right. I've got a big block of VHDL that synthesizes down to a decent size block of stuff, gated on the way out with synchronously cleared D flip-flops. I've looked over the RTL schematic and one of my signals cooks down, correctly, to:
FDR
.--o--. 1 --------------|D S Q'------------- OUT | | CLK --------------|> | | R Q| '--o--' | | SYNC_RST -----------------'
(created by AACircuit v1.28.5 beta 02/06/05
The rest have more exciting things going to the D input, but all are suffering from the same problem, which is that the flip-flops, while they sim correctly in the behavioral model, miss the first clock edge in all sims from Post-Translate on, that is after I drop the SYNC_RST line there is a rise, fall, rise on CLK before OUT goes high. Sounds like a setup timing problem, but CLK is only 20 MHz and SYNC_RST is low for a full 10 ns before the first rising edge. I realize the Spartan 3 isn't the fastest chip on the market, but 10 ns is still enough time for it to run to the corner store, pick up a cup of coffee, and still make it back in time for the edge.
I'm using ISE 6.3.03i and a freshly installed ModelSim Starter 6.0. Any ideas on what could be going on?
-- Rob