Problem with "don't care"

Hi guys! I'm experiencing same problems with don't care conditions in VHDL (with ISE / ModelSim)... I'm wondering if using don't cares in VHDL is a safe practice, since it seems that different tools treat them in different ways! For example, if I test "1110 0010" against "---- 0010" (with if, case, when and so on...) I expect to obtain a match, since the four specified bits are the same. The ISE (and maybe Synplify) seems to behave as expected when synthesizing the design, but ModelSim (behavioral sim.) does not recognize the two strings as the same (they are both std_logic_vector signals or constants). Is there somthing wrong I'm doing? It is better to avoid using don't cares at all? Ther is some kind of "workaround" to obtain the expected behaviour with ModelSim?!?

Thanks, Antonio

Reply to
A.D.
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A.D. schrieb:

In VHDL std_logic ist just an enumeration. So '-' does neither equal '0' nor '1'.

There are special library function that have the behaviour that you intend ('-' being equal to both '0' and '1'.)

There is another area where this can hurt you. The often used formulation if clock'event and clock='1' then ... to describe a rising edge triggered flip flop will misbehave in simulation because it will trigger on a change from 'U', 'X', '-' or 'H' to '1' (whicht it should not) but it won't trigger on a transition from '0' to 'H' or 'L' to 'H' (which it should). For simulation you really must use if rising_edge(clock) then ... instead.

Kolja Sulimma

Reply to
Kolja Sulimma

You need to use the std_match() function instead of the '=' operator.

KJ

Reply to
KJ

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