Hi guys! I'm experiencing same problems with don't care conditions in VHDL (with ISE / ModelSim)... I'm wondering if using don't cares in VHDL is a safe practice, since it seems that different tools treat them in different ways! For example, if I test "1110 0010" against "---- 0010" (with if, case, when and so on...) I expect to obtain a match, since the four specified bits are the same. The ISE (and maybe Synplify) seems to behave as expected when synthesizing the design, but ModelSim (behavioral sim.) does not recognize the two strings as the same (they are both std_logic_vector signals or constants). Is there somthing wrong I'm doing? It is better to avoid using don't cares at all? Ther is some kind of "workaround" to obtain the expected behaviour with ModelSim?!?
Thanks, Antonio