i am vinod..i got problem with ddr for virtex2 fpga. i have written code and did functional simulation everything is correct but after post translate simulation i am not getting same result. here is my code and testbench
code: library ieee; use ieee.std_logic_1164.all; library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity input_ddr is Port ( d : in std_logic; reset : in std_logic; clk : in std_logic; dataoutx : out std_logic; dataouty : out std_logic ); end input_ddr;
architecture input_ddr_arch of input_ddr is
signal q1, q2 : std_logic;
begin
process (clk,d,reset) begin
if reset = '1' then q1 ce,
d0 => risdatax, d1 => faldatax, r => '0', s => '0' );
clock1 : process begin clk