problem with DDR

i am vinod..i got problem with ddr for virtex2 fpga. i have written code and did functional simulation everything is correct but after post translate simulation i am not getting same result. here is my code and testbench

code: library ieee; use ieee.std_logic_1164.all; library UNISIM; use UNISIM.VCOMPONENTS.ALL;

entity input_ddr is Port ( d : in std_logic; reset : in std_logic; clk : in std_logic; dataoutx : out std_logic; dataouty : out std_logic ); end input_ddr;

architecture input_ddr_arch of input_ddr is

signal q1, q2 : std_logic;

begin

process (clk,d,reset) begin

if reset = '1' then q1 ce,

d0 => risdatax, d1 => faldatax, r => '0', s => '0' );

clock1 : process begin clk

Reply to
vinod
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Vinod,

I would guess that the reason you are seeing a functional difference would be due to the fact that you are not waiting until the global set/reset signal to complete. For all Xilinx gate-level simulations, a global set/reset pulse is generated for the first 100 ns of the design to initialize all of the registers and simulate the effect for the GSR signal in simulation. For the first 100 ns of the design, the registers will be in reset and will not change value. If you hold off you stimulus for the first 100 ns of simulation (keep your clock running and initialize the inputs but just don't wiggle them yet), you will likely see more correlation between your behavioral and post-translate simulation.

Also, if you are desiring to have the DDR register pulled into the I/O and use the dedicated resource, you should be instantiating the IFDDRRSE in the design. The code you are creating will use two separate registers but not the dedicated DDR registers in the I/O.

-- Brian

v> i am vinod..i got problem with ddr for virtex2 fpga. i have written

Reply to
Brian Philofsky

Brian Philofsky, Thank u for ur response..i made changes in my stimulus as u told stimuli : process begin wait for 20 ns; reset

Reply to
vinod

Vinod,

I do not fully understand your problem but I can guess that you may be having issues with order of events in the simulator other than what you are expecting. Try to offset your input stimulus from the clock so that the two do not happen at the same time to see if that makes things clearer as to how the logic operates. In other words try changing your input stimulus to change 1 ns after the clock edge and see if the results look more as you would expect.

-- Brian

v> Brian Philofsky,

Reply to
Brian Philofsky

Brian, Actually i mean if d is input port and data is coming to it at double data rate. in my code q1 and q2 are signals which takes data from d on risng and falling edges respectivley. ie. data in d on rising edge of clk shud come to q1(on falling edge of clk) and similarly data in d on falling edge of clk shud come to q2(on next rising edge of clk). timing diagram for input DDR is shown in this link.. page no : 225

formatting link

i am getting functional simulation correct but not gate level.. ie. data in d on rising edge of clk getting to q1 on same rising edge itself.similarly for q2. i think u can once simulate it and check it..

thank you vinod

Reply to
vinod

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