Problem with carry reusing RPM with ISE 6.2i and VirtexE

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Hi

First, excuse me for my english, Im a french student.

Then, I have problems to reuse RPM with ISE 6.2i and VirtexE :

I have cut a project in macros which are relationnaly placed.
I want to reuse those macros in another project but the Translate
shows me errors :
------ERROR:NgdBuild:753 - Line 3 in 'emis.ucf': Could not find
instance(s)
   'b_emisq/b_opp/Madd_s_inst_cy_34' in the design.  To suppress this
error
   specify the correct instance name or remove the constraint.
or
------ERROR:NgdBuild:753 - Line 4 in 'emis.ucf': Could not find
instance(s)
   'b_emisq/b_opp/Madd_s_inst_sum_34' in the design...
...

The carry logic and sum logic make errors because (I think) during the
resynthesise of the macros ISE changes the name of carry logic and sum
logic.

There's no error with the others logic, and I can reuse all macros
which have no carry chain.

Do you know those errors and how I can resolve them ?

Thank you

Yvan EUSTACHE

Re: Problem with carry reusing RPM with ISE 6.2i and VirtexE
Hi

First, excuse me for my english, Im a french student.

Then, I have problems to reuse RPM with ISE 6.2i and VirtexE :

I have cut a project in macros which are relationnaly placed.
I want to reuse those macros in another project but the Translate
shows me errors :
------ERROR:NgdBuild:753 - Line 3 in 'emis.ucf': Could not find
instance(s)
   'b_emisq/b_opp/Madd_s_inst_cy_34' in the design.  To suppress this
error
   specify the correct instance name or remove the constraint.
or
------ERROR:NgdBuild:753 - Line 4 in 'emis.ucf': Could not find
instance(s)
   'b_emisq/b_opp/Madd_s_inst_sum_34' in the design...
...

The carry logic and sum logic make errors because (I think) during the
resynthesise of the macros ISE changes the name of carry logic and sum
logic.

There's no error with the others logic, and I can reuse all macros
which have no carry chain.

Do you know those errors and how I can resolve them ?

Thank you

Yvan EUSTACHE

Re: Problem with carry reusing RPM with ISE 6.2i and VirtexE
Cher Yvan,
Two suggestions.
1) Use the Floorplanner to find out the new names of the chain, and correct
the UCF file accordingly.
2) Put the RLOCs in your source code. i.e. Use VHDL attributes. See the
'constraints guide' in the Xilinx documentation.
I've had to do both of these in the past.
Bon chance, Syms.
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