Problem to extend Xilinx GSRD Design

Hi i'm using the Xilinx GSRD design.

Now i try to connect a simple IP core to the reference design. The problem is that i can not connect my IP to the OPB or PLB bus. The 2 PLB Bus controllers supports only 1 Master and 1 Slave and they are alread connected.

The connection over the OPB does not work because they use a DCR2OPB bridge. May be the way over the DCR is a solution? How can i manage this connection. Are there some examples?

Eric

Reply to
tester
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You should switch over to the new MPMC2 based design which supports what you are looking for

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Ed McGettigan

-- Xilinx Inc.

Reply to
Ed McGettigan

Eric,

I am in the same boat. The workaround I found was to replace one of the plb_m1s1 cores with the standard plb_v34. So far this seems to have worked but I haven't finished the testing yet...

MPMC2 approach Ed mentioned would probably be a more natural approach but I didn't want to mess with replacing the memory controller as I wasn't sure it was fully compatible with the GSRD design...

/Mikhail

Reply to
MM

The latest (June 1st) release of the MPMC2 code base includes the equivalent of the original GSRD design using the new MPMC2 controller.

We haven't had time to update the GSRD page to note this release yet. You want to start with project/ml403_ddr_idpoc_100mhz_gsrd.zip file. The "_idpoc_" part denotes that the design uses the following interfaces:

i = ISPLB (connects to PPC405 I-side PLB) d = DSPLB (connects to PPC405 D-side PLB) p = PLB master (connects to general PLB arbiter) o = OPB master (connects to general OPB arbiter) c = CDMAC (connects to the TEMAC)

You should really upgrade to the new code base there is a lot more that you can do with this version.

Ed McGettigan

-- Xilinx Inc.

Reply to
Ed McGettigan

Thanks a lot Ed! It would be nice if you at least put a notice on the GSRD page. I've been waiting for this new release for quite a while... Anyways, I would be still interested to know whether the fix I applied to the original design would be expected to work?

Thanks, /Mikhail

worked

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Reply to
MM

If the workaround is what you described as "replace[ed] one of the plb_m1s1 cores with the standard plb_v34" then it probably still works. However, with the latest GSRD with MPMC2 design this isn't needed at all as you can build a MPMC2 core with bridges to PLB and OPB instead. This should result in a smaller and faster design than what you describe.

I agree that it would be a good thing to note on the GSRD landing page. I will ping the appropriate people on this and see if we can get it added.

Ed McGettigan

-- Xilinx Inc.

Reply to
Ed McGettigan

Yes, that's what I did. I was just a little worried that the 1 master/1 slave restriction resulted from some MPMC design limitation...

This is all great and I am definitely going to switch to the new design; my only problem at the moment is that I had to modify the ll_temac core to support RGMII mode and now I will have to figure out whether I have to do it all again or I can reuse my modified ll_temac core... Have you done anything to the ll_temac?

Also, at some point in the near future I will need to have two TEMACs connected to the same PPC... Could you tell me if this can be done in the new MPMC2 based design?

Thanks, /Mikhail

Reply to
MM

The current design was released with a GMII interface. We do plan on releasing a design with the RGMII interface, but there are other higher priority items on the plate right now. Since this is just the interface between the LL_TEMAC core and the IOs, you should be able to just use the same code that you have right now.

With MPMC2 you can have 2 or 3 or 4 LL_TEMACs in the design as the controller core now supports up to 8 ports of any type. There are hooks in the current LL_TEMAC design to support the dual mode, but we haven't released a pre-built design with this yet.

Ed McGettigan

-- Xilinx Inc.

Reply to
Ed McGettigan

I did some download and try the new MPMC2. Since I have Virtex4FX12 MiniModule I tried the MiniModule reference design (v4fx12mm_ddr_idpp_100mhz.zip) before I tried to modify the GSRD2 reference design, which is bult for ML403 (ml403_ddr_idpoc_100mhz_gsrd.zip). The v4fx12mm reference design IS NOT WORKING. I could not get anything from UART, which is like being blind for me. I contacted support and Glenn Baxter said to me that the design is thorougly tested. The design cannot work because there is at least one error in ddr_mem_test.c - UartBaseAdr is assigned with no value. I spend some more time on the design but still I couldn't get anything from UART (must be some HW error). Some more mails to mr. Baxter did'n help, so I quit trying and dedicate my time to my cores. I still wait for the solution. By the way: Glenn said that Linux support for GSRD2 is probably to be expected at the end of June. Is that true? Will we finally get the "real thing"?

Cheers,

Guru

Reply to
Guru

Out of curiousity: did you EVER have a GSRD implementation working on the MiniModule? I actually emailed Xilinx a while ago asking if this reference design would work on the MiniModule, and I was told that it would not due to several technical reasons (that were all enumerated at the time, and made sense to me, though I don't have them in front of me right now). So, I'd be curious to hear if you had the original GSRD working, and if you do in fact get the GSRD2 working.

Regards, John O.

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Reply to
john.orlando

Hi John,

You shocked me with your response. I have NEVER implemented an original GSRD to work on MiniModule. I actually did not find it necessary since I was waiting for GSRD2 (I tried to save some time). If there are some technical limits that prevent that I would like to see them written, because nobody told me yet, that this is not possible. I only had the original TEMAC reference design working (using LL_TEMAC in a CoreConnect style and lwip stack).

With regrets,

Guru

Reply to
Guru

Thanks for all that information!

It seems to me to be a good solution to change to GSRD2. Has anybody experiences if the current downloadable version will work with the Montavista Linux Preview Kit 3.1. I managed it to run it on GSRD1 design. I can reach about 120 Mbits/s now. If i change to the new one i have to get it run there with the same performance. My second approach is to use the DCR-Bus in the GSRD1. There is a Interrupt contoller connected to the DCR and i would like to do it like the source from there. Is there a chance that this works in the end? What do you think?

Eric

Guru schrieb:

Reply to
tester

Hi Eric,

Seems like MPMC2 implemented in GSRD2 opens unlimited possibilities to port the design to different platforms.

I have downloaded the latest version of MPMC2 (20060630) which also includes GSRD2 and there is no sign of Linux - only Treck IP stack, this time with source code.

Have you tested the performance of GRSD1 with Treck stack?

What do you want to connect to DCR bus? I hope not for data transmission, because it is a low performance bus, primary for registers reading/writing.

Send me a private email for further discussion/cooperation.

Cheers,

Guru

Reply to
Guru

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