Problem loading virtex2 FPGA in master serial mode.

We have a board with 2, Virtex6000 FPGA's that was working fine. Recently the boards stopped working and we saw that one of the FPGA's (lets call this as FPGA 1)was not being programmed. We are using separate bank of serial eeproms to load the FPGA's in master serial mode and they use the default 4 MHz serial clock frequency.

I checked the bit file in the eeproms and found that they passed the read/verify test using JTAG. But the FPGA would not load. Then I generated another eeprom file with 8 MHz serial clock frequency. The FPGA 1 magically started to work. Then when I tried loading the old file(4 MHz serial clock) it failed. Went back to 8Mhz it worked fine. Went back to 4MHz, it started working again and since then it has not failed.

In all probablity there is nothing related to the frequency of loading the bit stream. Maybe the board is flaky in terms of layout and power supply, de-coupling etc... Did anybody else have any such experiences?

On a side note, on a new batch of these boards the other FPGA (FPGA 2) frequently fails to load, while the FPGA 1 does not show any problems. Out of 5 boards fabricated 4 of them fail and only one board works fine.

This was first board with FPGA and large BF957 package for the engineer and the PCB layout person. Did they miss something?

This board is a PCI card. The 3.3V from the PCI bus is directly used as VCCIO and for VCCint there is a voltage regulator. Is there a problem in using 3.3v directly from a standard PC motherboard to power the FPGA I/O?

What could such a behaviour be attributed too?

Any pointers would be helpful.

Thanks. Brijesh

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Brijesh
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