Problem Instantiating a DSP48E or RAMB36 for a Virtex5 in ISE 8.2 SP2

I have tried to instantiate a DSP48E under ISE 8.2 SP2 but ISE does not recognize the part as a device primitive. Primitives are normal shown in red text under ISE but when I block copy the part from the language template the DSP48E is shown in black text and ISE does not know it is a primitive. I have a V5LX50 selected as the device I am using. I have also had the same problem instantiating a RAMB36 and a PLL_ADV. Does anyone know how to do this successfully?

Reply to
jeffnewcomb
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try LIBRARY UNISIM; USE UNISIM.Vcomponents.ALL; (assuming VHDL) Aurash

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Aurelian Lazarut

Reply to
jeffnewcomb

snipped-for-privacy@nci-usa.com schrieb:

if you cant use in verilog then just open a new schematic, place the DSP48E there add wires make wrapper and use from verilog code! defenetly works

Device Utilization Summary:

Number of DSP48Es 1 out of 48 2% Number of External IOBs 2 out of 220 1% Number of LOCed IOBs 0 out of 2 0%

Number of Slice Flip Flops 0 out of 28800 0% Number of Slice LUTS 0 out of 28800 0% Number of Slice LUT-Flip Flop pairs 0 out of 28800 0%

well at least with 8.2 (no SP)

Antti

Reply to
Antti

I think this is just a display issue. If the backend tools know dsp48e is a primitive, why bother if the text is shown in red or black?

HTH, Jim

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snipped-for-privacy@nci-usa.com wrote:

Reply to
Jim Wu

Reply to
jeffnewcomb

This is probably caused by something else as I just tried the code below and it works fine. Try to check the file encoding and make sure there is no weird characters in the file. I have seen problems with copying templates from PDF file.

module top(a_in, b_in, p_out); input [15:0] a_in; input [15:0] b_in; output [31:0] p_out;

DSP48E #( .ACASCREG(1), // Number of pipeline registers between A/ACIN input and ACOUT output, 0, 1, or 2 .ALUMODEREG(1), // Number of pipeline registers on ALUMODE input, 0 or 1 .AREG(1), // Number of pipeline registers on the A input,

0, 1 or 2 .AUTORESET_PATTERN_DETECT("FALSE"), // Auto-reset upon pattern detect, "TRUE" or "FALSE .AUTORESET_PATTERN_DETECT_OPTINV("MATCH"), // Reset if "MATCH" or "NOMATCH .A_INPUT("DIRECT"), // Selects A input used, "DIRECT" (A port) or "CASCADE" (ACIN port) .BCASCREG(1), // Number of pipeline registers between B/BCIN input and BCOUT output, 0, 1, or 2 .BREG(1), // Number of pipeline registers on the B input, 0, 1 or 2 .B_INPUT("DIRECT"), // Selects B input used, "DIRECT" (B port) or "CASCADE" (BCIN port) .CARRYINREG(1), // Number of pipeline registers for the CARRYIN input, 0 or 1 .CARRYINSELREG(1), // Number of pipeline registers for the CARRYINSEL input, 0 or 1 .CREG(1), // Number of pipeline registers on the C input, 0 or 1 .MASK(48'h3fffffffffff), // 48-bit Mask value for pattern detect .MREG(1), // Number of multiplier pipeline registers, 0 or 1 .MULTCARRYINREG(1), // Number of pipeline registers for multiplier carry in bit, 0 or 1 .OPMODEREG(1), // Number of pipeline registers on OPMODE input, 0 or 1 .PATTERN(48'h000000000000), // 48-bit Pattern match for pattern detect .PREG(1), // Number of pipeline registers on the P output, 0 or 1 .SEL_MASK("MASK"), // Select mask value between the "MASK" value or the value on the "C" port .SEL_PATTERN("PATTERN"), // Select pattern value between the "PATTERN" value or the value on the "C" port .SEL_ROUNDING_MASK("SEL_MASK"), // "SEL_MASK", "MODE1", "MODE2 .USE_MULT("MULT_S"), // Select multiplier usage, "MULT" (MREG => 0), "MULT_S" (MREG => 1), "NONE" (no multiplier) .USE_PATTERN_DETECT("NO_PATDET"), // Enable pattern detect, "PATDET", "NO_PATDET .USE_SIMD("ONE48") // SIMD selection, "ONE48", "TWO24", "FOUR12 ) DSP48E_inst ( .ACOUT(ACOUT), // 30-bit A port cascade output .BCOUT(BCOUT), // 18-bit B port cascade output .CARRYCASCOUT(CARRYCASCOUT), // 1-bit cascade carry output .CARRYOUT(CARRYOUT), // 4-bit carry output .MULTSIGNOUT(MULTSIGNOUT), // 1-bit multiplier sign cascade output .OVERFLOW(OVERFLOW), // 1-bit overflow in add/acc output .P(p_out), // 48-bit output .PATTERNBDETECT(PATTERNBDETECT), // 1-bit active high pattern bar detect output .PATTERNDETECT(PATTERNDETECT), // 1-bit active high pattern detect output .PCOUT(PCOUT), // 48-bit cascade output .UNDERFLOW(UNDERFLOW), // 1-bit active high underflow in add/acc output .A(a_in), // 30-bit A data input .ACIN(ACIN), // 30-bit A cascade data input .ALUMODE(ALUMODE), // 4-bit ALU control input .B(b_in), // 18-bit B data input .BCIN(BCIN), // 18-bit B cascade input .C(C), // 48-bit C data input .CARRYCASCIN(CARRYCASCIN), // 1-bit cascade carry input .CARRYIN(CARRYIN), // 1-bit carry input signal .CARRYINSEL(CARRYINSEL), // 3-bit carry select input .CEA1(CEA1), // 1-bit active high clock enable input for 1st stage A registers .CEA2(CEA2), // 1-bit active high clock enable input for 2nd stage A registers .CEALUMODE(CEALUMODE), // 1-bit active high clock enable input for ALUMODE registers .CEB1(CEB1), // 1-bit active high clock enable input for 1st stage B registers .CEB2(CEB2), // 1-bit active high clock enable input for 2nd stage B registers .CEC(CEC), // 1-bit active high clock enable input for C registers .CECARRYIN(CECARRYIN), // 1-bit active high clock enable input for CARRYIN register .CECTRL(CECTRL), // 1-bit active high clock enable input for OPMODE and carry registers .CEM(CEM), // 1-bit active high clock enable input for multiplier registers .CEMULTCARRYIN(CEMULTCARRYIN), // 1-bit active high clock enable for multiplier carry in register .CEP(CEP), // 1-bit active high clock enable input for P registers .CLK(CLK), // Clock input .MULTSIGNIN(MULTSIGNIN), // 1-bit multiplier sign input .OPMODE(OPMODE), // 7-bit operation mode input .PCIN(PCIN), // 48-bit P cascade input .RSTA(RSTA), // 1-bit reset input for A pipeline registers .RSTALLCARRYIN(RSTALLCARRYIN), // 1-bit reset input for carry pipeline registers .RSTALUMODE(RSTALUMODE), // 1-bit reset input for ALUMODE pipeline registers .RSTB(RSTB), // 1-bit reset input for B pipeline registers .RSTC(RSTC), // 1-bit reset input for C pipeline registers .RSTCTRL(RSTCTRL), // 1-bit reset input for OPMODE pipeline registers .RSTM(RSTM), // 1-bit reset input for multiplier registers .RSTP(RSTP) // 1-bit reset input for P pipeline registers );

endmodule

HTH, Jim

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snipped-for-privacy@nci-usa.com wrote:

Reply to
Jim Wu

Jim,

Thanks for the > This is probably caused by something else as I just tried the code

Reply to
jeffnewcomb

Yes, it runs through par w/o problem. Below is the map report: Slice Logic Distribution: Either LUT or Flip Flop pair used: 0 out of 28,800 0% Both LUT and Flip Flop pair used: 0 out of 28,800 0%

IO Utilization: Number of bonded IOBs: 64 out of 440 14%

Specific Feature Utilization: Number of DSP48Es: 1 out of 48 2%

HTH, Jim

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snipped-for-privacy@nci-usa.com wrote:

Reply to
Jim Wu

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