Hello all, While synthesysing the verilog module to generate clock of 12.5MHz from the default clock of XSA100 i.e 50MHz in ISE WebPack for XC2S100-TQ144 Spartan-II FPGA, I am getting an error. I have two inputs clock and reset and one output out. Here I go step by step:
i) Synthesis verilog code No error but the following warnings: =========================================================================
- HDL Synthesis * =========================================================================
Synthesizing Unit . Related source file is ddfs.v. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:646 - Signal is assigned but never used. INFO:Xst:1304 - Contents of register in unit never changes during circuit operation. The register is replaced by logic. WARNING:Xst:647 - Input is never used. WARNING:Xst:647 - Input is never used. Unit synthesized. =========================================================================
ii) Implement design works fine. But I am only seeing the signal out and not the clock and reset in the Pad Reports.
iii) Constraining the Fit: Create new Source (by right clicking on the verilog code file)Implementation constraints file..
iv) Open Xilinx Pace by clicking "Assign package pin". It gives a message "Top Level Block has pins that are not connected to any signals. Do you want them to treat them as user I/O?" I click "Yes"
v) Then I assign the pins P93 to reset, P88 to clock, P67 to out. And save it.
vi) Now when I click "Pad Report" to view the pin Assignment it gives me the following error;
**************************************************************************** Annotating constraints to design from file "ddfs.ucf" ... ERROR:NgdBuild:755 - Line 2 in 'ddfs.ucf': Could not find net(s) 'reset' in the design. To suppress this error use the -aul switch, specify the correct net name or remove the constraint. ERROR:NgdBuild:756 - Line 3 in 'ddfs.ucf': Could not find net(s) 'reset' in the design. To suppress this error specify the correct net name or remove the constraint. ERROR:NgdBuild:755 - Line 6 in 'ddfs.ucf': Could not find net(s) 'clock' in the design. To suppress this error use the -aul switch, specify the correct net name or remove the constraint. ERROR:NgdBuild:756 - Line 7 in 'ddfs.ucf': Could not find net(s) 'clock' in the design. To suppress this error specify the correct net name or remove the constraint. ERROR:Parsers:11 - Encountered unrecognized constraint while parsing. ERROR:NgdBuild:19 - Errors found while parsing constraint file "ddfs.ucf".Writing NGDBUILD log file "fulladd28.bld"... ERROR: NGDBUILD failed Reason:
Completed process "Translate".
*******************************************************************************here is the verilog code:
******************************************************************************* `timescale 1ns/1ps module fulladd28(out,clock,reset); parameter a=28'd67108864; parameter w = 28; // bit width of phase accumulator output out; input clock, reset; reg [w-1:0] sum; always @(posedge clock or posedge reset) if(reset) sum