Hi everyone,
I have a problem that is bugging me for 2 days now and I was hoping someone here might be able to help me out. The problem is as follows: I want to implement a DDR2 RAM Controller in a Xilinx Virtex 4 FX FPGA on the Xilinx ML410 eval board. It's supposed to run at 200 MHz, which I want to derive from the on-board 100 MHz oscillator. For this I need to use 2 DCMs cascaded (1 to get to 200 MHz, and the second one for all the other frequencies the RAM controller [generated with MIG 1.6] needs (main problem is the 200 MHz shifted by 90 deg). The first one works perfectly fine, only the second one never locks. Even in a module with just the 2 DCMs and Clock Buffers it fails to work. All the clocks fall well within the ranges of the modes I use and everything is connected as recommended by Xilinx. I use the CLK2X output of the first one to specifically avoid excessive jitter, I delay the config done flag until the first one has locked, I use the inverted lock output of the first one to reset the second one with a shift register in between. I already tried to manually place the DCMs at specific locations and impose timing constraints on the signal in between. The interesting thing is that the CLKFX output seems to work fine, I checked that on a scope, only the others fail to work. And even more interesting, 1 week ago I implemented a DDR RAM Controller in which I used exactly the same structure except that it was running at 160 MHz and I didn't have any problems at all. If I try to do same now, it still doesn't work!! So after about 20 hours of trying I just ran out of ideas. Maybe someone of you has another idea.
Cheers, Michael