Hello all,
I'm using the Xilinx Viterbi decoder IP (V5) in serial mode with standard parameters (conv 7 1/2 with codes 0 and 1 default, input soft
8-bit words signed, traceback length 42, no treillis, no puncturing).I've made a convolutional bit encoder (7 1/2) for making patterns to test the viterbi decoder and I switched to 8 bits by coding '1' as strongest ones (FF) and '0' as strongest zeros (7F).
The Xilinx Viterbi decoder is decoding fine in RTL simulation with Modelsim but when I launch the simulation after P&R, I don't get the same results, and those I get are completely different from what I should get. I tryed to launch the simulation with lower clk period (60 MHz), but the results are the same, so the problem is not coming from timing errors.
I have also tried to switch from serial to parallel mode, using the CE input as the input enable signal. It's still working fine in RTL simulation, but the problem remains the same after P&R, and the IP becomes much bigger (2380 slices instead of 730 in serial mode) and doesn't hold the timing anymore (XST estimation is 103 MHz vs 148 in serial mode; my design constraint is 140 MHz, my target is a V2P70-6).
As anyone experienced the same problem and know how to solve it ?
Thanks a lot for your answers.
Regards,
Arnaud