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Problem about clock switch in Quartus II 6.0

I use Cyclone II to implement image processing. There are a CMOS image sensor, a FPGA chip, and a SRAM on my board. I meet a new problem when I try to optimize my design. In my old instance, I use the same clock when image capture (storage), image display, and image processing. This clock, which is named "pclk", has a frequency of 24MHz. It is slow. The frequency of image capture and display cannot be changed because of the requirement of other device. So I want to increase the frequency of image processing. It involves SRAM reading, writing, and data processing. I use a PLL to acquire a clock of 72MHz. This is the problem. SRAM will also be read when image capture, and written when display. That means the clock, the address bus and data bus will be switched between the state of image capture/display and image process. Actually, I use two blocks: one for image capture/display and another for image process. And I use BUS MUX to switch address bus and data bus. Meanwhile, I use LPM MUX to switch the two clock of different frequency. Unfortunately, the instance does not meet timing. In Timing Analyzer Summary, it reports, Clock setup: 'pclk' has a slack of

-4.152ns and Clock hold: 'pclk' has a slack of -4.216ns. What should I do to solve this problem?

Best Regards, X.Y.

Reply to
X.Y.
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X.Y. wrote: I use two blocks: one for image capture/display and another

If I had to actually switch the clock rather than use the preferred clock enables, I would make separate capture and process entities and run timing separately.

A clean switch-over must be guaranteed somehow by design. Maybe handled by software.

--- Mike Treseler

Reply to
Mike Treseler

Assuming you are using the Classic Timing Analyzer, make sure you have a CUT assignment between the two clock domains. In the QSF, you want to see something like:

set_instance_assignment -from pclk -to - name CUT ON set_intance_assignment -from -to pclk -name CUT ON

You can make these assignments using the Assignment Editor.

BTW, clock muxing is something the new TimeQuest Timing Analyzer does very well. Here is an example of how to describe this in an SDC for TimeQuest:

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Hope this helps.

-David Karchmer Altera

Reply to
dkarchmer

Thanks for your reply! I use Classic Timing Analyzer. I want to try the CUT assignment. Unfortunately, I meet new problem. I right-click on the pclk pin and select locate in assignment editor. Then I select CUT Timing Path in the "assignment name" category and select the pll clock name in the "from" category. After that, I click save icon. Curiously, what I just assigned disappears. I open the QSF file, there is no my CUT assignment. How can I save my constraint setting?

Best Regards. X.Y.

Reply to
X.Y.

X.Y.,

Quartus caches all the QSF information in memory, so even when you click on save, you are just saving the Assignment Editor changes into the in-memory QSF database. Quartus will automatically write out the newest QSF when you either close the project (or revision), or start a back-end process ("Compile" "Start Fitter", "Start Classic Timing Analyzer", etc).

-David Karchmer Altera

Reply to
dkarchmer

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