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Hi, I learn VHDL. I got text: "

Compiling 'komp.vhd' in 'H:\PROGRAMY\WARP\BIN'. VHDL parser (h:\programy\warp\bin\vhdlfe.exe V4 IR x66) Library 'work' => directory 'lc16r4' Library 'ieee' => directory 'h:\programy\warp\lib\ieee\work' Using 'h:\programy\warp\lib\ieee\work\stdlogic.vif'. High-level synthesis (h:\programy\warp\bin\tovif.exe V4 IR x66) Synthesis and optimization (h:\programy\warp\bin\topld.exe V4 IR x66) Design optimization (dsgnopt) Equation minimization (minopt) Design optimization (dsgnopt) Device fitting (pla2jed) Error: Polarity specified for LHS signal y must be Active Low. "

Code I was trying to synthes is:

"library ieee; use ieee.std_logic_1164.all;

entity komparator is port (a,b,c: in std_logic; y: out std_logic); end komparator;

architecture komparator of komparator is begin

yiuyuiku:process(a,b,c) begin y

Reply to
zlotawy
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Wojtek,

It looks like you are using VHDL to program a small PAL part?

The error message seems to indicate that the part cannot represent the logic in your equation without first using DeMorgan to generate an active low output. I don't understand why VHDL isn't able to do this for you.

The last time I used parts like this I was programming in PALASM. the equation would look like !Y = !A + !B + !C where "+" was the OR operator in PALASM.

Maybe your synthesizer wants you to write:

not y Hi,

Reply to
Gabor

The problem is that the 16R4 isn't HDL-friendly; use a 16V8 instead. (Do they even sell 16R4's anymore?)

Re-coding it like this might work:

Y
Reply to
ghelbig

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Thank You so much!

It works. I do not understand what is the difference between 16R4 and 16V8 and more others, but it works and i am gratefull :-)

Wojtek

Reply to
zlotawy

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