Historically, std_logic_unsigned/signed is vendor proprietary and there have been differences between vendors treatment of those libraries.
ieee.numeric_std is an honest standard, and won't give you grief if you have a mix of signed and unsigned in the same entity, and behaves the same regardless of whose tools you use. Use that.
btw, to_integer belongs with ieee.numeric_std, and conv_integer goes with std_logic_unsigned/signed.
Crap...I hate making little typos like that. Anyway thanks, I had thought the numeric_std was the way to go, and ghdl's author/community was pushing in that direction as well, I just wanted confirmation.
Now I need to switch back to the numeric_std, since I had gone the other way just to get the projects integrated...
-Dave
--
David Ashley http://www.xdr.com/dash
Embedded linux, device drivers, system architecture
A) library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all
fine. But when I try to integrate it with code that uses:
B) library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all;
Everything goes to crap. I use unsigned in my new code, but the existing code's "unsigned" doesn't match, they don't link up. Meaning I can't port map entities from my code using (A) into the project that uses (B).
There is a lot of existing code, such as a model for a ddr: mt46v16m16.vhd
which I need for simulation. That all uses (B).
How can I get around this problem? I tried converting the code that uses (B) into using (A), but it's over my head and was just creating one compile error after another...
To get it to build I converted my code to (B) and that works fine (and is easy) but I don't want to start down the dark path...
Thanks--
-Dave
--
David Ashley http://www.xdr.com/dash
Embedded linux, device drivers, system architecture
Probably you can try to change the interfaces between modules to use only std_logic (or std_ulogic, depending on what you want to do) and only use signed/unsigned for the internal signals. In fact, some people insist on this approach/style emphasizing that the interfaces only carry logical values and the "interpretation" of what these logical values actually mean, should only be done inside the modules.
Change the ports on all the entities to std_logic or std_ulogic and std_logic_vector or std_ulogic_vector, then assign the signed/unsigned inside, that way they are compatible with either library.
Right...that makes sense. All the trouble is appearing because my interface uses unsigned. That will do very nicely, and all I need to do is modify my interface. Thanks very much everyone who responded!
-Dave
--
David Ashley http://www.xdr.com/dash
Embedded linux, device drivers, system architecture
ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here.
All logos and trade names are the property of their respective owners.