Precision Synthesis verilog netlist black box question

Hey,

Just wondering if anyone knows the command to stop module declarations of black boxes being written out to the verilog netlist precision generates for post-synthesis simulation.

At the moment i'm having to trawl through my post synthesis netlist and delete the empty module declarations. It's annoying and lengthy (as there are many).

There must be some attribute i can set to false or a command to halt precision writing out these empty module declarations I just cant seem to find it in the documentation.

Any help would be amazing.

Cheers,

Rob.