Precision RTL and DesignWare libraries

Hi,

I was wondering if anyone had any experience with using Synopsys' DesignWare libraries in a Precision RTL FPGA flow? I am especially interested in the automatic conversion of DW RAM devices to Altera blocks, but I am also curious about the use of the other components as well (arbiters, fifos, etc.). I assume the specific components will be instantiated (and simulated) using a black box methodology, but what happens after that, how do I push these components all the way down to my FPGA?

Thanks,

-- Edmond Cot=E9

Reply to
Edmond Coté
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I was wondering if anyone had any experience with using Synopsys' DesignWare libraries in a Precision RTL FPGA flow? I am especially interested in the automatic conversion of DW RAM devices to Altera blocks, but I am also curious about the use of the other components as well (arbiters, fifos, etc.). I assume the specific components will be instantiated (and simulated) using a black box methodology, but what happens after that, how do I push these components all the way down to my FPGA?

From what I understand from the manual, Precision supports a wide range of the datapath and logic DesignWare modules. If you use a non-supported module then you will end up with a blackbox. You then need to provide the RTL/EDIF for this block before going to P&R.

If Precision can translate all your Designware blocks then you can of course use the Altera primitive libraries for any simulation, however, if you get any blackboxes then as far as I know the only option you have is to use VCS but I might be wrong,

Hans

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Thanks,

-- Edmond Coté

Reply to
HT-Lab

ule

IF

That's what I would assume, but does it make any sense. If you specify a specific adder in the middle of your datapath, how does Precision accurately resolve its timing (pre-PNR)? The other option that I can think of, is that Precision automatically converts all the DW blackboxes to its own primitives, but that is a flat out guess..

rse

CS

That shouldn't be an issue, you can find the DesignWare blocks somewhere in $SYNOPSYS/dw and compile them yourself.

-- Edmond Cot=E9

Reply to
Edmond Coté

Not sure I understand you here, we are talking about ASIC prototyping using an FPGA right? This is no different than sticking an adder in your FPGA design, the timing gets resolved using the (close to useless :-) wireload model.

Correct, Precision converts DW blocks to "functional equivalent" FPGA blocks and if it can't then you get a blackbox.

Cool, didn't know that. I assume the copyright notice prevents one from using it on anything else but Synopsys products?

Hans

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Reply to
HT-Lab

ng

Right, but wouldn't knowing that the blackbox resolves to an adder, rather than a counter, produce a better timing estimate?... No need to answer this, I'm simply trying to think through the mechanics of how this all works.

cks

Ok, that answered my original question, thank you!

My hunch is that their license can't be *that* restrictive. I took a look at the behavioral models and they seemed pretty standard to me.

-- Edmond Cot=E9

Reply to
Edmond Coté

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