I was wondering if anyone had any experience with using Synopsys' DesignWare libraries in a Precision RTL FPGA flow? I am especially interested in the automatic conversion of DW RAM devices to Altera blocks, but I am also curious about the use of the other components as well (arbiters, fifos, etc.). I assume the specific components will be instantiated (and simulated) using a black box methodology, but what happens after that, how do I push these components all the way down to my FPGA?
From what I understand from the manual, Precision supports a wide range of the datapath and logic DesignWare modules. If you use a non-supported module then you will end up with a blackbox. You then need to provide the RTL/EDIF for this block before going to P&R.
If Precision can translate all your Designware blocks then you can of course use the Altera primitive libraries for any simulation, however, if you get any blackboxes then as far as I know the only option you have is to use VCS but I might be wrong,
Hans
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Thanks,
-- Edmond Coté