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PPCs sharing an OCM BRAM

I have run into a roadblock with my project. Trying to get the PPCs in the V2P to share a BRAM. I have gotten it to work via the PLB bus (both PPCs with their own bus, each bus connected to the same BRAM), but haven't been able to make it work via the DSOCM. I followed pretty much the same steps to connect both DOCM buses to the same BRAM as I did for the PLB set up, but it seems that writes are not working. I get no errors, but every write fails (can check the contents via XMD--always 0x0). Tried looking at some Xilinx-provided designs for clues/inspiration to no avail.

Is there some nuance to the OCM stuff that I am missing? I have gone through the OCM documetation, but if anyone thinks they know what I have missed or what I need to do to fix this, I would appreciate any advice. I can provide more details if helpful...

Thanks,

Joey

Reply to
Joseph
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Have you simulated the design?

Paul

Joseph wrote:

Reply to
Paul Hartke

Not yet. There is no custom logic whatsoever, so I didn't bother. It seemed that poking around with XMD would be sufficeint debugging until I added custom blocks.

Joey

Reply to
Joseph

Well, it turns out that I didn't hook the reset or clk signals up to the 2nd DOCM bus (the first one was set up automatically by the Base System Builder). For *some* reason it didn't want to work without a clock--touchy little bus, huh? : )

Thanks for the read/response, Paul. And thanks to anyone who spent any time reading this... I am sure I will be back before too long...

Joey

Reply to
Joseph

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