Hi,
Hopefully I can be of assistance despite your use of an inferior part ;-p
You mention 1.3W of power @ 104C, presumably at room temperature (25C) and nominal (1.2V) voltage with still air and no heatsink, measured on the case (?). How are you arriving at 1.3W? Is this just the current draw off VccInt x 1.2V? Remember that there is also current drawn off VccAux (65 mA * 2.5V = 163mW according to XPE). And assuming you have I/Os in your chip, there will additional power drawn from your VccO (for all I/O standards) and off-chip Vtt rails (if using terminated standards) -- more on that later.
Assuming your 1.3W is correct, then you've got a ThetaCA (case-to- ambient thermal resistance) of (104-25) / 1.3 = 60 degrees per W!!! That seems unlikely, so I will assume that there is some additional source of power dissipation in your FPGA. With no air movement, I'd figure a thetaJA of ~15 deg/W is more reasonable (based on Cyclone III EPE). Assuming this is the case, you are burning somewhere in the neighbourhood of (104 - 25) / 15 = 5.3W in your FPGA (eek). I think you need to find that power source!
First, I would check to be 100% certain that your I/Os are not shorted or nothing else bad like that is happening. Shorted I/Os (for example, unused I/Os driving ground but hooked up to a signal or vcc on the board) can really burn a ton of power. Measure your device temperature with the clocks completely disabled so that the only contributors are static core and static I/O power -- what's the temperature? Then run with the I/Os clocked correctly, but disable as much core logic functionality as possible.
Even if your I/Os are not shorted, it would help to describe your I/O configuration. I/Os can burn a lot of power. Unterminated I/O standards (such as 3.3V LVTTL) will consume power to charge and discharge the (a) FPGA pin (b) PCB trace and (c) far-end load; all of this current draw is dissipated as heat inside the FPGA, and is irrespective of drive strength and slew rate (well, almost -- these will affect the short-circuit current, but unlikely to be more than a
10% impact).
Terminated I/O standards are a whole other beast. There is a static current drawn through the voltage-divider network formed by your I/O drive transistor, the series termination resistor, and the near/far- end parallel termination resistor to Vtt. This is true regardless of whether you are driving a 1 or a 0. Only some of that current draw is dissipated as heat within the FPGA -- the rest is dissipated in off- chip components. This means that your *thermal power* will depend on the drive strength of your SSTL I/O -- the higher the drive, the higher the *system power* consumption but the lower the *FPGA thermal power* will be.
You can download the Cyclone II or Cyclone III Early Power Estimator to play around with I/O standards and see how much power is dissipated on vs. off-chip for various configurations of I/O. All the data in that tool is from HSPICE simulations of our I/O buffer, and we've carefully seperated out on-chip power from system power/current draw. While Spartan-3 will have slightly different I/Os, they should behave similarly to first order so the trends/results should be good enough for your purposes. The tool is available at
formatting link
If you verify that indeed you aren't burning a ton of I/O power, next step is the core. This is trickier -- the best things you can do are to set clock enables on the global clocks, set clock enables on the FFs (which disables some local clocking), and only read/write to your RAMs when you really need the data. For example, don't be lazy with your FIFOs -- if you aren't using the read port on a given cycle, disable the read enable / clock enable on the block. You can also try area-driven synthesis (vs. speed or balanced mapping). This will result in smaller circuits which will tend to use less power (but not always).
Hopefully you'll respond with some more information on your design and your measurements. If all else fails and your design really is running at 104C, and you can't slap a heat sink on it (without fan), then I'd suggest taking the bluer road and migrate your design to Cyclone III :-)
Regards,
Paul Leventis Altera Corp.