Power PC Reference Design timing failed

Recently, I download a reference design from Xilinx. Then implementate in EDK9.1.02i, while checking the timing report,I find some fails,such as:

------------------------------------------------------------------------------------ Constraint|Check| Worst Case | Best Case | Timing | Timing | | Slack | Achievable | Errors | Score

------------------------------------------------------------------------------------

• TS_dc | SET | -0.598ns | 6.196ns | 300 | 59028 m_1_dcm | UP | _1_CLK0 | _BUF = | PERIOD | HOLD| 0.410ns | | 0 | 0 TIMEGRP| "dcm_1_ | dcm_1_CL| K0_BUF" | TS_dcm | _0_dcm_0 | _CLK2X_B| UF HIGH |

50% | /////////////////////////////////////////////////////////////////////////////////////////////////////

• TS_dcm |SET | -0.197ns | 5.262ns | 6 | 848 _1_dcm_ |UP |

1_CLK90_ | BUF = P | ERIOD |HOLD| 0.446ns | | 0 | 0 TIMEGRP | "dcm_1 | _dcm_1_ | CLK90_B | UF" | TS_dcm | _0_dcm_ | 0_CLK2X | _BUF P | HASE | 1.25 ns | HIGH | 50% | ///////////////////////////////////////////////////////////////////////////////////////////////////// during this report the best case has enough slack,but the worst case fail the constraints.Has anybody encounter this case,and how to solve it,any advices are welcome,thanks.