Is a case study in which the latest claims of power savings by the competitor's software are debunked.
I had intended to post this as part of the earlier thread, but I couldn't find the link to the above white paper.
If you ignore the superiority of Virtex 4, and just concentrate on the improvement in power from the tool, going from ~ 2.8 watts to ~ 2.6 watts, or an improvement of 200 mW, is roughly an improvement of 7% less power.
So, routing and placement can really save some power. Or perhaps, one should say poor routing and poor placement can increase power?
Or should one say that Virtex 4 uses so much less power, that talking about how much is 'saved' by the software tool is just a distraction to fool the unwary?
Energy consumption is rapidly eclipsing original product acquisition cost when doing a total life-time cost analysis. For each Watt the IC consumes, an additional 2-3 Watts are consumed in power conditioning, conversion and cooling.
It has long been known that appropriate placement and routing at the physical layer can save power (not by a huge amount, but certainly of the order of 5% or so depending on the circumstances). I've done a lot of high speed design work, and minimising power is always an issue.
To find it can be done internally with the place and route tool is not particularly surprising - indeed it is to be expected. I wonder when the optimisation goal will be expanded to include 'power' (instead of just speed and space).
Why are the power values measured at 25C and than scaled, in a way that is not given in the paper, to 85C. Either provide the values at 25C for reference or measure at 85C.
Another point: measurements are nice, but what about the worst case values?
Martin, You did read this? "We collected power data at 25°C junction temperature from idle (0 MHz) up to 200 MHz, in 50Mhz steps. We then scaled the results to 85°C using static power data previously taken on Virtex-4 and Stratix II devices over temperature (see Xilinx White Paper WP223 for further information). Note that previous testing has shown that dynamic power does not vary significantly with temperature for either family of devices. " Cheers, Syms.
idle (0 MHz) up to 200 MHz, in 50Mhz steps. We then
Virtex-4 and Stratix II devices over temperature (see
has shown that dynamic power does not vary
I did read this and that is exactly the point I want to criticize. I don't like measuring an aspect at one temperature point, not showing the results, but scaling it 'in some way' to a different temerature point for the final graph.
However, it's not so important - just a little bit of marketing stuff ;-)
No, Martin, it is not Marketing, it is Science. Dynamic power and static power (leakage) have different temperature dependencies: Dynamic power is independent of temperature (since the frequency and the capacitance do not change), while leakage current is very temperature dependent. The two can be added linearily. Therefore it is not necessary to measure dynamic power at temperature.
And let this quibbling not obfuscate the basic fact: Xilinx power consumption is much lower than Altera's. We have to mention this because Altera makes so much noise about their (non-existent) power superiority. Their claims are just Marketing BS...
Let's say inbetween. The description of the method in the Xilinx paper is not self contained. And the initial criticism still holds: Where are the numbers at 25C?
About scientific relevant measurements: How many different FPGAs (from different production runs) have been measured for this paper?
Ok, thanks for the clarification. But in this paper the overall power was measured at 25C and the static power was added from some other source for the 85C figure.
Didn't want to say that this is not correct, just a few thoughts about methods in the Xilinx paper.
Martin, I find it hard to be patient with you. If dynamic power is constant with temperature, and static power increases monotonically with temperature, and total power is always the linear sum of static and dynamic power, then I can scientifically state that
Total Power @85 = static power @85 + dynamic power @25 degrees.
And that is not Marketing. (Which we all agree is almost a dirty word in our circles).
Well, not quite. Your results DO clearly show a reduction in power ?!
Perhaps what you meant to say, was "reality checked, and compared with alternate devices" What is does show, is the mA/MHz slopes are now very similar.
It also shows that in the Xilinx test case, Static Icc dominates, and alerts designers to possible ommision of that detail in Altera's stats and claims.
Why all this commotion? It does not take a genius to interpret the graph:
Dynamic power is very similar for the two competing devices, although Xilinx has still an edge, even after the Altera improvements. The dramatic (>2:1) difference is in static power consumption, which of course is ugliest at 85 degrees. Here Xilinx benefits from its use of three different gate oxide thicknesses (Altera uses only two). And, to camouflage their weakness, Altera conveniently published those meaningless 25 degree total power numbers. That's what I mean by Marketing BS, for most devices in the Virtex-4 or Stratix-II class are operated at high clock rates, which makes them run hot, close to and sometimes even above 85 degrees. To brag about allegedly low power at 25 degrees misses the point, is Marketing BS. Peter Alfke, from home. Happy New Year. whichever FPGA you prefer.
On this one design selected by Xilinx marketing, your graph shows similar dynamic power between Stratix II and Virtex4. See
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for power results across a large suite of designs. Hardware measurements over designs of various types show that Stratix II has lower dynamic power on 80% of the designs, with *Quartus 5.0*. Quartus 5.1 reduces dynamic power by an average of 20% when you turn on extra effort power-driven compilation, and have a testbench, so that further widens the advantage here. See
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for a netseminar detailing the power optimization features in Quartus 5.1, and a dynamic power comparison between Stratix II and Virtex4 using Quartus 5.1.
Hardware measurments in the white paper listed above also show Stratix II has lower I/O power than Virtex4. Virtex4 has lower static power, but the advantage here is not huge, once you include the significant Vccaux power that Xilinx marketing literature neglects, and use worst-case process static power numbers.
Since total power is the sum of these three components, there is a variation in which device has the lower total power depending on your device utilization and clock frequency. At moderate to high utilization, and the clock frequencies typical for a 90 nm FPGA, Stratix II generally has lower total power. At sufficiently low clock frequencies and low device utilization, Virtex4 will have lower total power.
All of these hardware measurments can be reproduced at the customer site with a board that has both a Stratix II and Virtex4 device on it, with identical board design parameters for both. The source code for the designs can be inspected by the customers to ensure we aren't biasing the results to favour Stratix II. Contact your FAE if you'd like a demo -- so far we haven't had any customer who hasn't found the demo both fair and compelling.
The white paper above, and all data on Stratix II and Cyclone II power at
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and
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respectively, compare static power at 85 C, worst-case process.
It is totally unclear how the white paper you reference computes static power. It appears to be a single-unit measurement at 25 C, scaled using an unknown methodology to 85 C. I also suspect that once again it does not include Vccaux static power for Virtex4, since the graph shows the V4 unit measured as having ~600 mW of static power, while the Virtex4 web power tool shows that typical static power for Virtex4 (including Vccaux) is 868 mW, and worst-case is 1.53 W.
As I stated above, all the Altera power comparisons include and highlight the 85 C, worst-case silicon static power comparison. The Xilinx white paper, by comparison, uses an unknown methodology to compute static power, and produces a number that is below both the typical and worst-case specification for Virtex4. I'll let the readers of the newsgroup decide which comparison has more engineering validity.
The power optimization features in Quartus II 5.1 target dynamic power. The reduction in dynamic power shown on your graph is 19%, which is definitely of interest to most of our customers. The white paper above does not appear to have included a testbench for the Quartus II compilation -- that reduces the effectiveness of power-driven compilation somewhat. So with a testbench, I would expect some further power reduction.
As this design is relatively small (~40% logic utilization, less than 20% overall RAM utilization for Stratix II), the dynamic power consumed is lower than typical. Customer designs are almost always more full than this, and often operate at clock frequencies above 200 MHz. In such cases dynamic power obviously goes up, while static power doesn't, so dynamic power becomes a larger part of total power and you would see more than the 7% total power reduction seen here.
See my reply to Peter later in this thread for a complete summary of the competitive power picture between Stratix II and Virtex4, and an analysis of the weaknesses of this white paper.
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