Power on reset generation in FPGA

Hi all,

I have a question on POR(Power on reset generation ) using FPGA. My FPGA does not have a external Power ON reset , i am planning to generate a Power ON reset in the FPGA only.Is it really feasible to do this in an FPGA, and use this as the reset for my logic. Any suggestions appreciated??

Regards, Prav

Reply to
praveen.kantharajapura
Loading thread data ...

schrieb im Newsbeitrag news: snipped-for-privacy@g44g2000cwa.googlegroups.com...

sure its possible. it is maybe not always as good as external reset circuit but for most cases its ok.

the FPGA actually does release itself from reset during powerup configuration, if needed you can delay it to generate a longer reset

Antti

Reply to
Antti Lukats

As Antti mentions, most FPGAs nowdays have an asynchronous power on reset built in. Assuming you want an internal synchronous reset, just create a large counter which is will count down once after an asynchronous reset. A synchronous reset would be held until the counter finishes (of course, don't apply the synchronous reset to the countdown counter;)

Reply to
Duane Clark

built in. Assuming you

count down once

counter finishes (of

I'd suggest not using "1111...11"s or "000...0"s as the terminal count. If you've no external asynch reset to intiialise this counter you can't be sure what state it'll be configured to power up in. I'd suggest that all '1's or all '0's are the two most likely power up states.

Use "101010...1010" as your termninal count and the odds are the flip-flops won't power up to match it.

Nial

------------------------------------------------------------- Nial Stewart Developments Ltd FPGA and High Speed Digital Design

formatting link

Reply to
Nial Stewart

Duane,

Xilinx FPGAs use the prog_b pin to act as an external reset if you prefer. Asserting prog_b to ground will cause the device to hold off configuration. Releasing prog_b will allow the device to configure, and start up.

Aust>

built in. Assuming you

count down once

counter finishes (of

Reply to
Austin Lesea

I'm not exactly sure what the original poster was asking, but I use an SRL16(xilinx) initialised to X"FFFF", configured as 16 bit shift reg, and a '0' at the D input. Once Done goes high, GWE, GSR, etc are released(order of these dependent on bitgen options), the shift reg shifts in the '0' and after 16 clock cycles it appears at the SRL16 Q output. The Q output drives the reset I code into my design(active high). This insures my design reset is removed synchronous to my clock and the path is covered by my clock period timing constraint.

(beware that the GSR net is high fanout and can have significant delay/skew depending on your clock frequency. I never found any timing specs for the GSR net in the Sparatan 3 FPGA datahseet...but there are plenty of posts about it. There is also a good tech exclusive(ken chapman) on the xilinx site talking about the use of resets in your FPGA design.)

Regards Andrew

Reply to
Andrew FPGA

built in. Assuming you

count down once

counter finishes (of

Actually, the power up state on most FPGAs is determined by the bit stream. For Xilinx, flip-flops that have a set or preset input default to '1' on power up, all others default to '0'. You can change individual flip-flops by using the INIT attribute and generic. In any event, the power up state is deterministic. And get this: If you have an externally applied asynchronous reset, you can actually make that non-deterministic if you are not careful to have the design come synchronously out of reset. Consider the case where you have a free-running binary counter that gets reset to all '1's by an async reset. The next state of the counter is all zeros, however if you release your async reset close to the active clock edge, some of the counter bits will get thier reset released at that clock edge, and some won't, and will therefore remain reset for one more clock cycle. The result is your initial count is not consistently all '1's depending on where the falling edge of reset occured with respect to the clock edge and the differences in the routing delays and set-up times to the individual flip-flops in the counter. An asynchronous reset is an ansynchronous signal and must be properly synchronized by your design in order to obtain consistent results. This is an alarmingly frequent design error (and it is not due to metastability as some have suggested). Generally speaking, asynchronous resets are a very bad idea in FPGAs. Not only does this design error often trap the unwary, the async reset also slows down the fabric of the FPGA because of the design concessions that were made in the flip-flops to include the async reset.

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
 Click to see the full signature
Reply to
Ray Andraka

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.