Hi I am using a Spartan XC3S400 FPGA. Initially after poweron one particular signal read_enable does not get enabled. It is a simple logic. There is just one additional signal controlling it. And this control signal has the expected status level as i observed with chipscope. But the read_enable signal does not act until the system is resetted. This read enable signal is connected to the input of asynchronous FIFO.
Once resetted there are no problems. My question is, is there some way on how to find out why the signal is behaving differently by looking at the schematic by the Xilinx after synthesis . And whether has it got to do something with being connected to the Asynchronous FIFO. Are the FIFO inputs tristated after the FPGA is configured from the PROM on poweron until resetted. The asynchronous FIFO is from Xilinx Coregen.
Thank you for your help
regards vasu