Potential Uses of Atmel FPSLIC Devices?

Here are some applications:

************************************************* Octal Fixed 9600 BAUD UART for external MCU. Common BAUD RATE generator

FPGA implements a 2 bit shift register for each tranmitter FPGA implements a majority voting filter and a startbit detector on each receivers FPGA synchronizes the receiver data with the transmitter data. Octal Software UART using a single interrupt handling all 8 transmitters and all 8 receivers handling H/W or S/W flow control Maintaining error counters

4 kB SRAM for FIFO buffers (256 level FIFO in both directions)

Thís should fit into the AT40K05.

**************************************************** Low speed HDLC controller (16 kbps) on T1/E1 line.

FPGA implements a synch serial controller with timeslot assignment. AVR handles the bit stuffing, calulcates CRC etc.

****************************************************** Advanced Timers Multiple capture channels. You have up to 16 kB x 8 SRAM for capture data. You can run the AX series in 40 Mhz. This means that you can store 8 x 40 = 320 bits of capture info per microseconds. If you capture 96 bits with a 64 bit timestamp you need 160 bits or 20 bytes giving you 500 ns resolution. you can store a maximum of 16384 / 20 = 819 events.

The SRAM can store sinus waveforms, for easy waveform generation.

***************************************************** If you need a fieldbus, here is the part. Many companies have their proprietary serial bus, which is often a piece of cake to implement on the FPSLIC. **************************************************** Graphics LCD controller. 64 * 128 = 1024 bytes. Fits easily into the FPSLIC and you get high speed access to the LCD buffer. **************************************************** CMOS camera framegrabber. Implement the CCITT interface in the FPGA Add a 32 x 15 FIFO in FreeRAM, and store in a shared memory outside the FPSLIC.

---------------------- Generally things which needs slow processing and fast synchronisation are excellent applications for the FPSLIC:

Feel free to contact me directly.

--
Best Regards,
Ulf Samuelsson
ulf@a-t-m-e-l.com
This message is intended to be my own personal view and it
may or may not be shared by my employer Atmel Nordic AB

Implementing filters is another possibility. You have lots of SRAM in an otherwise small FPGA:

I think it should be possible with a 100 ns 16 x 16 -> 32 multiply + 32 bit accumulate in 4 clocks on a 5/10 kgate FPSLIC, with both sample and coefficient in the n x 8 SRAM.

The AVR can acquire the samples from an external ADC and then start FIR/IIR filtering.

--
Best Regards,
Ulf Samuelsson
ulf@a-t-m-e-l.com
This message is intended to be my own personal view and it
may or may not be shared by my employer Atmel Nordic AB

Ulf,

I'm having trouble replying to you directly. Is your mail address correct.

snipped-for-privacy@a-t-m-e-l.com

Or am I being stupid!!