I am trying to do a Virtex4 design, I have completed the post synthesis (XST) simulations in Modelsim - everything appears fine. When I run the PAR and simulate the generated model. I get all zeros on the output. None of the registers in the desing appear to be loading. I have specified the timing constraints for the period of the clock (only that constraint). Is there something I may be forgetting to do? My desing is runnig at 125Mhz.
Thanks