Post PAR simulation is successful but still fails on the board

Hi,

I am using a Virtex II development board and am doing some work with a little system on a chip. I am using onboard block RAM as both the instruction ROM and RAM for programs. I was going along fine until I added some more code for the processor to run, which made the executable too big for the RAM I had created. I simply doubled the size of the RAM to allow the extra space.

Everything looked fine in behavioral simulation, so I went ahead and put it on the board. The results weren't as expected, so I looked at the simulation again. I did a post place-and-route simulation at the clock speed of the target device and it worked perfectly. I have since gone back to older code and the smaller memory and things work most of the time. Occasionally I seem to get no output, but I can usually fix it by clearing the project files, restarting the Xilinx software, and resynthesizing my design.

Has anyone experienced anything like this before? It doesn't seem like using more of the block RAM should have any effect on the rest of the design. In my searching before I posed this I came across a topic called "Xilinx BRAM failures" that talked about bitfiles working on some chips and not others due to problems with the BRAMs. Is this a possibility? Or maybe there was a static discharge problem at some point that damaged one or more slices or BRAMs that would cause it to fail?

Thanks for any suggestions you might have!

Reply to
longbrmb
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Ok, you can ignore my question above. I did some more experimenting and it turns out I was somehow doing the post PAR simulation wrong. I think closing the project navigator software must have cleared something out because the next time I ran the simulation I got numerous timing failures that were obviously causing my problems.

Reply to
longbrmb

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