Hi All, I am currently developing for Xilinx SPARTAN3 FPGA. I have a design in which a FSM asserts a clock enable signal for few registers (all registers use the same clock-enable) for 1 clock cycle. My post place and route simulation shows correct operation of the design i.e the registers are updated correctly. However when I run the design on actual FPGA the registers are not updated and design doesn't behave correctly.
I extended the clock enable to 2 clock cycles and this makes the design run correctly on the FPGA.
I have done post PAR timing analysis and don't get any timing errors. I am also clocking the device at half the clock speed that the design can be run at. I am not sure what the problem is. Would anybody please be able to tell me what the problem might be.
Thanks for your help. Sudhir