post-fit simulation failed

Hello,

with the following code snipped I have Problems on synthese/fit process on xst Web/ISE 8.1 (the behavioral simulation works fine) for a CPLD XC95000:

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Reply to
Olaf Petzold
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maybe, the fitter report may help:

Reply to
Olaf Petzold

"Olaf Petzold" schrieb im Newsbeitrag news:dqvdse$jnd$ snipped-for-privacy@viper.mdlink.de...

[snip]

Hi Olaf,

this is what 8.1 does from your code (I copy pasted your code with NO mods!!), XC9500 as target

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arm

Reply to
Antti Lukats
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Thanks Antti,

using the same (with sp1)

Reply to
Olaf Petzold

"Olaf Petzold" schrieb im Newsbeitrag news:dqvj42$kfi$ snipped-for-privacy@viper.mdlink.de...

Dear Olaf,

1) do not try to oversmart the tools, it doesnt work. I do not know what you are doing, but when I tested your code in new project all default setting all worked properly.

2) it looks like the code you have trouble is part of logic analyzer - so call me killjoy, but XC95xx is not a part you would use for logic analyzer, so select suitable device and the problem you are having would not be there at all.

doing a logic analyzer (a simple one) is really piece of cake. doing a good one just means doing the specifications the implementation is not an issue at all.

I just feel that you have spend a lot of your time in your logic analyzer project without having anything useable to demonstrate so far.

I just dont have enough fingers (only 37 on last count) to implement some logic analyzer properly, I would do it targettable to any Xilinx FPGA using configuration readback (capture storage reading ) and partial reconfiguration (for trigger settings).

Antti

Reply to
Antti Lukats

Hi, Olaf: Please complete all the state in your if-else statement.

"Olaf Petzold" ??????:dqvdse$jnd$ snipped-for-privacy@viper.mdlink.de...

Reply to
Sophie Liu

"Olaf Petzold" schrieb im Newsbeitrag news:dqvdse$jnd$ snipped-for-privacy@viper.mdlink.de...

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Hi Olaf,

sorry - I did not pay enough attention to "8.1" - I do have 8.1 installed as secondary ISE so I tested your code on 7.1

the code does invoke a PLD fitter bug that is new to 8.1, that is your code works correctly when target arch is FPGA or ISE version is 7.x or earlier.

with XC95xx as target and 8.1 the input signal does get optimized away as you describe. so I have added it to the public bug track database :)

antti

Reply to
Antti Lukats

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