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Possible bug in Vertex-4 Rocket-IO?

I need to use Rocket-IO in Vertex-4 to receive data at the rate of

6.22Gbps. My reference clock input to the Rocket-IO is 155.5MHz. Data rate is 40X of that clock. I need to have a parallel output in 40-bit-wide format and output at 155.5MHz rate. I do not need any other process inside the Rocket-IO. I just need to do serial-to-parellel conversion. I have followed the guide of Rocket-IO and also got some help from Xilinx engineer to get a start. Now I have simulated with VCS to see the Rocket-io output data as I intended to.

However if I run the simulation longer I see the parallel output become incorrect at every 40th parellel output word. The expected value is not there. Instead the value in the previous clock cycle is repeated. This goes on at every 40th word. All other output words are correct.

I am wondering if any other V4 Rocket-IO user faces the same problem. Could it be the simulation model's problem, Xilinx Rocket-IO's bug, or something I did not set up correct? Unfortunately the same Xilinx engineer keeps quite since I sent my question to him. Maybe too busy?

Appreciated for any help. If needed I can send all the files including instantiation to GT11 and testbench. These are verilog files.

Reply to
shuo.huang
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Reply to
Marko

Reply to
shuo.huang

So, you are getting more clocks output than you are inputting? This must be the case if you are repeating codes. I guess the other possibility is that you are inadvertently sending the same code twice and your receiver is working properly.

Reply to
Marko

Reply to
shuo.huang

So, you get word 1-38, 39, 39, 41, 42 ... Is that correct? You repeat word 39 and skip word 40?

Is the problem data dependent? If you change the data, is the effect the same?

Do you have a comma alignment character embedded?

Is this a single channel application or are you bonding multiple channels together?

Reply to
Marko

The problem is not data dependent. I did not enable comma alignment. This is a single channel application.

Did you have succesfull experience with similar settings?

Reply to
shuo.huang

Forgot to confirm your first paragraph. Yes. That is the pattern I see in the simulation.

Thanks for your help.

Reply to
shuo.huang

I had good luck with Rocket IO in Virtex2Pro. I used comma alignment, bonded two channels together and use the recovered clock to clock everything in the receiver (except the refclk). My bit rate was only about 1Gbps. In my case, everything worked in simulation and in hardware.

If you don't use comma alignment, how to you align the serial stream to the word boundary? Are you using a standard protocol or custom?

You say this happens in simulation. I presume you don't have hardware? I presume you purchased the smart model extension for ModelSim? If so, can you get support from ModelTech and/or Xilinx on this issue? Have you followed all the rules for proper simulation. One rule I remember was that simulation must run at pico-second speed.

Sorry I can't be of more help.

Reply to
Marko

Thanks Marko for sharing your experience.

I do not use comma alignment inside the Rocket-IO. I have circuit after it to do the alignment. I am planning to use Virtex-4 device (if it works). I do not think there is any hardware available yet.

I used VCS (from Synopsys) to simulate. It takes smartmodel as well. I am trying to get help from Xilinx for a number of weeks. But I have not got any helpful solution yet.

I noticed that in Roket-IO model the time scale (time unit definition in Verilog) is defined in ps. I tried to modify my test bench from ns to ps. Nothing was changed. In Verilog it is allowed to have different time scales in different modules. I think the simulation with smartmodel settings should be correct, because otherwise it would not work at all. It would not be only at every 40th output.

Thanks for your time. I will post the final result when I have it.

Reply to
shuo.huang

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