Pointer to a good article on clock domain crossing

Hi Philip, Thanks for the link! As you say, a pretty good article. There's one little thing I'd like to say! I prefer the circuit Rick presented here on CAF over the one presented in fig.3. Search Google Groups for subject "Async logic in FPGAs" in comp.arch.fpga . Rick's circuit works well even if the signal to be synchronised can clock faster than the synchronising clock. Of course, some of the faster clock's transitions can still be missed, but any burst of, for example, two fast clocks on the input signal will (almost*) always be caught by at least one clock enable in the synchronised domain. A practical example of this is debouncing a switch input with a slow clock. Imagine a key switch input being sampled at 1kHz. The circuit in Fig.3 could miss the key press if the bouncy signal has an even number of rising edges. Rick's circuit gets the bugger (almost*) everytime! Cheers, Syms.

• Metastability is always possible, no matter how remote that possibility. In the 1kHz example the synchronising circuit could stay metastable for 1ms!

Or in the archive at

I agree, Rick's design is a better way to pass the flag than Roy's figure 3.

I have added links to both of these articles, and also some articles by Peter Alfke at the end of the FAQ page on metastables at

Thanks again for the ref to a good article,

Philip

=================== Philip Freidin snipped-for-privacy@fpga-faq.com Host for