Hello,
I am trying to use PLX9056 as an interface between PCI bus and local bus, in manner as simple as possible. I would fill some SRAM on the local bus with certain amount of data (256 or 8K or 32K or 64K words) from uP or FPGA and then tell PLX to take that data and transfer it to PCI bus. The transfer may also need to go in the opposite direction, i.e. PLX filling the SRAM and telling my uP/FPGA that the data is ready. Arbitration may be handled on local bus side by an FPGA, but I do not know how to establish the communication between uP/FPGA and PLX.
Is there a group of registers where size of data for burst transfer can be defined? How to tell PLX that the data is ready for transfer? How does the PLX tell uP/FPGA on local bus that data has arrived from PCI bus?
Help would be greatly appreciated.
Regards,
Alex