I need a vhdl code for a pll.....or any of its components......like a freq divider...VCO.....loop filter and phase detector...thanks
Is there anyway that the pll could be implemented onto a FPGA chip.
I need a vhdl code for a pll.....or any of its components......like a freq divider...VCO.....loop filter and phase detector...thanks
Is there anyway that the pll could be implemented onto a FPGA chip.
This question has been asked before (search the archives at fpga-faq.com) Anyway, the answer depends on the kind of PLL you're looking for. RF PLL? No. PLL to get a clock for on-chip or off-chip use? Many FPGAs include onboard PLLs (Xilinx offers what they call a DLL, makes use of a string of inverters with a mux to set the delay). These are pre-built sections you can use. If you need this for low-frequency applications (where all the analog signals are sampled, for example a video signal), you can use Coregen to generate all the required portions (VCO -> NCO, loop filter -> FIR core, phase detector -> multiplier). -Jim
Xilinx has a phase detector in a app. note. The dividers should be quite easy to implement. The VCO and loop filter will have to be outside the FPGA.
Leon
Thanks.....What I am looking for is a PLL to get a clock for off chip use.......I am actually using it for a video application where I am trying to genlock. Please let me know if have any ideas abt this.....
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So all you can do inside the FPGA are the prescalers and the phase/frequency detector. Have a look at the datasheet of the good old 4046, there you find everything. The VC(X)O and the loop filter will still be classic analog parts.
Regards Falk
Thanks...Well, right now...everything is working with the whole PLL function being done inside the FPGA itself.....but then there is a jitter in the output.....and am not able to figure out the reason....
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How much jitter?
1ns? 1us?Whats the output frequency of the VCO? Whats the compare frequency of the phase detetor?
Regards Falk
Is there a way to measure the jitter?...the ouptu frequewncy of the VCO is 27Mhz....and the input frequency is 15.34 Mhz....so the PLL's dividers are given ratios accordingly...
Falk Brunner wrote:
reason....
Look back to my previous post. The phase comparator of the PLL should have two inputs at 15.734 kHz. One comes from the sync stripped off your video, the other from the VCO divider in the FPGA. Sync your scope on one, crank the timebase speed and the brightness way up, and see how far the other jitters.
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