PLL clock in in Stratix

hello,

I would like to use the PLL with a clock frequency below 4 MHz. But when I use the MegaFunction under Quartus, it says me that the minimum input clock frequency is 15 MHz.

Is there an alternative to do a clock multiplication ?

I would like to clock multiply the input frequency. I know that to have lower frequency that the input, I can just do clock divider, but me I want clock multiplier !!

Thanks. Best regards