Hello (world),
I've a dodgy problem with a plb_sdram_v1_00_c connected to the PLB with a PowerPC as single master and a second slave (a plb2opb_bridge).
The SDRAM is a HYB/E 25L128160AC 128-MBit-Mobile-RAM at a Memec-X2VP7-Eval-Board. I use the settings as stated in the appendix (the really interesting part of this posting). They are taken from a tutorial design that comprise a OPB-sdram (and already worked with a coregen generated sdram controller connected to a selfmade opb-like bus).
Writing to the SDRAM works fine. Reading from SDRAM yields an error ratio of about 800/4194304: In the error cases the 9th Bit of data is '1' instead of '0'. A second subsequent read from an "error address" gives the correct data value.
Obviously (?) it's some kind of timing problem. The timing report says that the overall period constraint is met. The only thing that perplexes is:
WARNING:Timing:2666 - Constraint ignored: PATH "FROM U_CLK TO D_CLK" TIG ;
(Xilinx-Answer says it can be safely ignored)
Thanks to those how read this posting (and even the appendix) and thanks to any kind of advice
Christian
(The APPENDIX:) PARAMETER C_SDRAM_REFRESH_NUMROWS = 4096 PARAMETER C_SDRAM_TMRD = 2 PARAMETER C_SDRAM_TCCD = 1 PARAMETER C_SDRAM_TRAS = 48000 PARAMETER C_SDRAM_TRC = 70000 PARAMETER C_SDRAM_TRFC = 75000 PARAMETER C_SDRAM_TRCD = 19000 PARAMETER C_SDRAM_TRRD = 16000 PARAMETER C_SDRAM_TRP = 25000 PARAMETER C_SDRAM_TREF = 64 PARAMETER C_SDRAM_CAS_LAT = 2 PARAMETER C_SDRAM_COL_AWIDTH = 9 PARAMETER C_SDRAM_BANK_AWIDTH = 2 PARAMETER C_SDRAM_AWIDTH = 12 PARAMETER C_SDRAM_DWIDTH = 32