PLB-IPIF and user IP interface problem

I have a problem in initiating a PLB _IPIF back to back transactions.

I have integrated my IP backend with PLB-IPIF.

My IP is User master while initiating transaction and then completes the transaction as slave, on IPIF side.

Once I am done with Write transaction initiated on PLB bus from IP Master interface(through IPIF) and after receiving last_ack, I am initiating another write transaction, but its fails to respond!

The status after 1st write transaction is that Bus2IP_BE shows 80h and Bus2IP_CE shows IP master chp enable asserted. What does it mean?

I found nothing related to this in PLB_IPIF_V2_01.pdf

Can anybody help me out in understanding the disconnects?

Reply to
Ashish
Loading thread data ...

Any body has updates on this????

Ashish wrote:

Reply to
Ashish

Thanks Guys for not replying to my problem.(May be I would have got diverted.... :) )

I am able to solve the problem I was facing.

Just for somebody's ref.

My IPIF transaction IP Master signals were extending to next clock after last ack and that was causing problem in initiating back to back transactions.

PLB_IPIF took my IP master signals (asserted for one clock after de assertion of Last_ack) as new transaction request and my state machine went to dead lock. That also caused PLB_IPIF Ip slave attachment Statemachine to go in busy state and I was not able to complete more than one write transactions!!!!!!!

This I could solve by wiring the IPMaster signals INSTAED of flopping.

Thats it...

regards

Ashish

Ashish wrote:

Reply to
Ashish

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.