PLB DDR Controller : Sl_rearbitrate issue

Hello,

Sometime back there was a question on the comp.arch.fpga about interfacing a PLB master pcore with the PLB DDR controller (see below for thread or check this out:

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. Recently, I have set-up a simulation environment in which my master pcore talks a PLB DDR controller (instead of a PLB BRAM). My master pcore issues 384 writes to the PLB DDR controller, then it reads from the locations it wrote. My master pcore successfully completes all 384 writes, then it starts the reads. On the 109th read, it encounters the exact same problem as described in the posting. Anyone encountered this issue and fixed it? I have been avoiding using PLB_DDR in simulation, but I have some apps that use too much memory and cannot fit in the conventional PLB BRAMs.

Thanks,

NN

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Nju Njoroge
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Nju Njoroge

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