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Planahead IP export

Hi,

I'm trying to insert an IP core generated by PlanAhead into our script-based flow, but map fails with Pack:679 error on several slices.

The IP in question is a wrapper around the PCIe block plus, that contains our DMA engine. This component is pretty big and we decided to lock it down when we deliver the sources to our customers. Using PlanAhead, we intend to floorplan it tightly and lock its placement so the customer won't have timing issues.

The exported IP is in the edn/ucf form, and it's imported into our xst flow without problems. I gutted the top level of the component and made it a black box. Xst and ngdbuild run without problems. Both transform the edn into an ngo. I also concatenated the system ucf to the component ucf and fixed the relative paths.

Map fails with 105 error 679, and over 3 thousand warnings (some expected). Different runs give different results though.

"Unable to obey design constraints (LOC=SLICE_X46Y115) which require the combination of the following symbols into a single SLICEL component" ... (snip - see below) "The clock enable signals don't agree. Please correct the design constraints accordingly."

Looking at the SLICEL in PlanAhead, I see six symbols (3 LUTs, 3 FLOPs) and a seventh one that doesn't seem related to the others. Perhaps this is the one "clock enable" referred to in the error message.

Also, doubting of the import-into-my-flow procedure, I made another PA project, where I import this same IP into the netlist, and it fails with the same errors.

Has anybody seen this error? The answer records show some similar errors, but no explanation on how to work around it/fix it.

Thanks in advance,

-Pat

Error Message:

------------------------------ ERROR:Pack:679 - Unable to obey design constraints (LOC=SLICE_X46Y115) which require the combination of the following symbols into a single SLICEL component: LUT symbol "ii_pci_express_interface/application_reg_file/mmux_ctl_reg_o_sig_60_mux00003

11" (Output Signal = ii_pci_express_interface/application_reg_file/ctl_reg_o_sig_60_mux0000[8]) LUT symbol "ii_pci_express_interface/application_reg_file/mmux_ctl_reg_o_sig_60_mux00003 21" (Output Signal = ii_pci_express_interface/application_reg_file/ctl_reg_o_sig_60_mux0000[9]) LUT symbol "ii_pci_express_interface/application_reg_file/mmux_ctl_reg_o_sig_62_mux00003 11" (Output Signal = ii_pci_express_interface/application_reg_file/ctl_reg_o_sig_62_mux0000[8]) FLOP symbol "ii_pci_express_interface/application_reg_file/ctl_reg_o_sig_60_8" (Output Signal = ctl_reg) FLOP symbol "ii_pci_express_interface/application_reg_file/ctl_reg_o_sig_60_9" (Output Signal = ctl_reg) FLOP symbol "ii_pci_express_interface/application_reg_file/ctl_reg_o_sig_62_8" (Output Signal = ctl_reg) The clock enable signals don't agree. Please correct the design constraints accordingly.
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PatC
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Hello Pat,

We have seen similar map issues in the past when sending large amounts of LOC constraints via a UCF file to ISE. We've made some improvements in both 10.1 ISE and PlanAhead to address them. Rather than just passing LOC constraints, we've seen a much better success rate when passing both LOC and BEL constraints. Therefore, in 10.1 release of PlanAhead, we've defaulted both the Export IP and Export Pblock commands to include both types of constraints in the UCF. The map group has also fixed quite a few of these types of logic packing scenarios that cause packing failures.

I'm not sure what version of PlanAhead you are using, but the latest

9.2 versions will output BEL constraints. If you are using 9.2, we'd like to try it using 10.1 PlanAehad and ISE. It would be helpful if you could file a bug against PlanAhead with the design data. If we duplicate it here, it will be filed as a bug against the map tool.

The other option is to strip out the 105 lines in question from the UCF file. We find that the mapper with usually just put them back in the same locations anyhow???

Please fell free to contact me directly to help resolve the issue.

Brian Jackson Marketing Manager, Xilinx

720-652-3102

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Reply to
brian.jackson

FWIW,

Brian, thanks for your input.

I could solve this map issue by disabling global optimization when building the IP block to be exported. Once the IP is inserted in the destination design, global_opt can be enabled again, if needed.

-P@

snipped-for-privacy@xil> Hello Pat,

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PatC

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